974
986
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
976
pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
988
pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
977
989
rxdw0 = le32_to_cpu(val);
978
pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
990
pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
979
991
rxdw1 = le32_to_cpu(val);
980
pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
992
pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
981
993
rxbufLO = le32_to_cpu(val);
982
pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
994
pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
983
995
rxbufHI = le32_to_cpu(val);
985
997
DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
1048
1060
/* receive/copy to target memory */
1049
1061
if (dot1q_buf) {
1050
pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1051
pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1062
pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1063
pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN,
1052
1064
buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1053
1065
size - 2 * ETHER_ADDR_LEN);
1055
pci_dma_write(&s->dev, rx_addr, buf, size);
1067
pci_dma_write(d, rx_addr, buf, size);
1058
1070
if (s->CpCmd & CPlusRxChkSum)
1109
1121
/* update ring data */
1110
1122
val = cpu_to_le32(rxdw0);
1111
pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1123
pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1112
1124
val = cpu_to_le32(rxdw1);
1113
pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1125
pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1115
1127
/* update tally counter */
1116
1128
++s->tally_counters.RxOk;
1294
1306
static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1308
PCIDevice *d = PCI_DEVICE(s);
1296
1309
RTL8139TallyCounters *tally_counters = &s->tally_counters;
1297
1310
uint16_t val16;
1298
1311
uint32_t val32;
1299
1312
uint64_t val64;
1301
1314
val64 = cpu_to_le64(tally_counters->TxOk);
1302
pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
1315
pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
1304
1317
val64 = cpu_to_le64(tally_counters->RxOk);
1305
pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
1318
pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
1307
1320
val64 = cpu_to_le64(tally_counters->TxERR);
1308
pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
1321
pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
1310
1323
val32 = cpu_to_le32(tally_counters->RxERR);
1311
pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
1324
pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
1313
1326
val16 = cpu_to_le16(tally_counters->MissPkt);
1314
pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
1327
pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
1316
1329
val16 = cpu_to_le16(tally_counters->FAE);
1317
pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
1330
pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
1319
1332
val32 = cpu_to_le32(tally_counters->Tx1Col);
1320
pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
1333
pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
1322
1335
val32 = cpu_to_le32(tally_counters->TxMCol);
1323
pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
1336
pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
1325
1338
val64 = cpu_to_le64(tally_counters->RxOkPhy);
1326
pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
1339
pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
1328
1341
val64 = cpu_to_le64(tally_counters->RxOkBrd);
1329
pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
1342
pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
1331
1344
val32 = cpu_to_le32(tally_counters->RxOkMul);
1332
pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
1345
pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
1334
1347
val16 = cpu_to_le16(tally_counters->TxAbt);
1335
pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
1348
pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
1337
1350
val16 = cpu_to_le16(tally_counters->TxUndrn);
1338
pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
1351
pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
1341
1354
/* Loads values of tally counters from VM state file */
1822
1839
DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1841
PCIDevice *d = PCI_DEVICE(s);
1824
1842
int txsize = s->TxStatus[descriptor] & 0x1fff;
1825
1843
uint8_t txbuffer[0x2000];
1827
1845
DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1828
1846
txsize, s->TxAddr[descriptor]);
1830
pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
1848
pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
1832
1850
/* Mark descriptor as transferred */
1833
1851
s->TxStatus[descriptor] |= TxHostOwns;
1960
1979
uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1962
pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1981
pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1963
1982
txdw0 = le32_to_cpu(val);
1964
pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1983
pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1965
1984
txdw1 = le32_to_cpu(val);
1966
pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1985
pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1967
1986
txbufLO = le32_to_cpu(val);
1968
pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1987
pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1969
1988
txbufHI = le32_to_cpu(val);
1971
1990
DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
3270
3292
.post_load = rtl8139_post_load,
3271
3293
.pre_save = rtl8139_pre_save,
3272
3294
.fields = (VMStateField []) {
3273
VMSTATE_PCI_DEVICE(dev, RTL8139State),
3295
VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
3274
3296
VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3275
3297
VMSTATE_BUFFER(mult, RTL8139State),
3276
3298
VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3475
3497
static int pci_rtl8139_init(PCIDevice *dev)
3477
RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3499
RTL8139State *s = RTL8139(dev);
3500
DeviceState *d = DEVICE(dev);
3478
3501
uint8_t *pci_conf;
3480
pci_conf = s->dev.config;
3503
pci_conf = dev->config;
3481
3504
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3482
3505
/* TODO: start of capability list, but no capability
3483
3506
* list bit in status register, and offset 0xdc seems unused. */
3484
3507
pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3486
memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3487
memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
3488
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3489
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3509
memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3511
memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s,
3513
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3514
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3491
3516
qemu_macaddr_default_if_unset(&s->conf.macaddr);