139
139
finish_read_pci_config(spapr, buid, addr, size, rets);
142
static void rtas_read_pci_config(sPAPREnvironment *spapr,
142
static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
143
143
uint32_t token, uint32_t nargs,
144
144
target_ulong args,
145
145
uint32_t nret, target_ulong rets)
206
206
finish_write_pci_config(spapr, buid, addr, size, val, rets);
209
static void rtas_write_pci_config(sPAPREnvironment *spapr,
209
static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPREnvironment *spapr,
210
210
uint32_t token, uint32_t nargs,
211
211
target_ulong args,
212
212
uint32_t nret, target_ulong rets)
439
440
qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
442
static uint64_t spapr_io_read(void *opaque, hwaddr addr,
447
return cpu_inb(addr);
449
return cpu_inw(addr);
451
return cpu_inl(addr);
456
static void spapr_io_write(void *opaque, hwaddr addr,
457
uint64_t data, unsigned size)
461
cpu_outb(addr, data);
464
cpu_outw(addr, data);
467
cpu_outl(addr, data);
473
static const MemoryRegionOps spapr_io_ops = {
474
.endianness = DEVICE_LITTLE_ENDIAN,
475
.read = spapr_io_read,
476
.write = spapr_io_write
480
444
* MSI/MSIX memory region implementation.
481
445
* The handler handles both MSI and MSIX.
509
static DMAContext *spapr_pci_dma_context_fn(PCIBus *bus, void *opaque,
473
static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
512
475
sPAPRPHBState *phb = opaque;
477
return &phb->iommu_as;
517
480
static int spapr_phb_init(SysBusDevice *s)
482
DeviceState *dev = DEVICE(s);
519
483
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
520
484
PCIHostState *phb = PCI_HOST_BRIDGE(s);
521
485
const char *busname;
582
546
/* Initialize memory regions */
583
547
sprintf(namebuf, "%s.mmio", sphb->dtbusname);
584
memory_region_init(&sphb->memspace, namebuf, INT64_MAX);
548
memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, INT64_MAX);
586
550
sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname);
587
memory_region_init_alias(&sphb->memwindow, namebuf, &sphb->memspace,
551
memory_region_init_alias(&sphb->memwindow, OBJECT(sphb),
552
namebuf, &sphb->memspace,
588
553
SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
589
554
memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
590
555
&sphb->memwindow);
598
563
* system_io works around the problem until all the users of
599
564
* old_portion are updated */
600
565
sprintf(namebuf, "%s.io", sphb->dtbusname);
601
memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
566
memory_region_init(&sphb->iospace, OBJECT(sphb),
567
namebuf, SPAPR_PCI_IO_WIN_SIZE);
602
568
/* FIXME: fix to support multiple PHBs */
603
569
memory_region_add_subregion(get_system_io(), 0, &sphb->iospace);
605
571
sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
606
memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb,
607
namebuf, SPAPR_PCI_IO_WIN_SIZE);
572
memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
573
get_system_io(), 0, SPAPR_PCI_IO_WIN_SIZE);
608
574
memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
609
575
&sphb->iowindow);
613
579
* from msi_notify()/msix_notify() */
614
580
if (msi_supported) {
615
581
sprintf(namebuf, "%s.msi", sphb->dtbusname);
616
memory_region_init_io(&sphb->msiwindow, &spapr_msi_ops, sphb,
582
memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, sphb,
617
583
namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000);
618
584
memory_region_add_subregion(get_system_memory(), sphb->msi_win_addr,
619
585
&sphb->msiwindow);
631
597
* since it's unique by construction, and makes the guest visible
636
602
} else if (sphb->index == 0) {
639
605
busname = sphb->dtbusname;
641
bus = pci_register_bus(DEVICE(s), busname,
607
bus = pci_register_bus(dev, busname,
642
608
pci_spapr_set_irq, pci_spapr_map_irq, sphb,
643
609
&sphb->memspace, &sphb->iospace,
644
610
PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
647
613
sphb->dma_window_start = 0;
648
614
sphb->dma_window_size = 0x40000000;
649
sphb->dma = spapr_tce_new_dma_context(sphb->dma_liobn, sphb->dma_window_size);
615
sphb->tcet = spapr_tce_new_table(dev, sphb->dma_liobn,
616
sphb->dma_window_size);
651
618
fprintf(stderr, "Unable to create TCE table for %s\n", sphb->dtbusname);
654
pci_setup_iommu(bus, spapr_pci_dma_context_fn, sphb);
621
address_space_init(&sphb->iommu_as, spapr_tce_get_iommu(sphb->tcet),
624
pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
656
626
QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
693
663
DEFINE_PROP_END_OF_LIST(),
666
static const VMStateDescription vmstate_spapr_pci_lsi = {
667
.name = "spapr_pci/lsi",
669
.minimum_version_id = 1,
670
.minimum_version_id_old = 1,
671
.fields = (VMStateField []) {
672
VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi),
674
VMSTATE_END_OF_LIST()
678
static const VMStateDescription vmstate_spapr_pci_msi = {
679
.name = "spapr_pci/lsi",
681
.minimum_version_id = 1,
682
.minimum_version_id_old = 1,
683
.fields = (VMStateField []) {
684
VMSTATE_UINT32(config_addr, struct spapr_pci_msi),
685
VMSTATE_UINT32(irq, struct spapr_pci_msi),
686
VMSTATE_UINT32(nvec, struct spapr_pci_msi),
688
VMSTATE_END_OF_LIST()
692
static const VMStateDescription vmstate_spapr_pci = {
695
.minimum_version_id = 1,
696
.minimum_version_id_old = 1,
697
.fields = (VMStateField []) {
698
VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState),
699
VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState),
700
VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState),
701
VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState),
702
VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState),
703
VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState),
704
VMSTATE_UINT64_EQUAL(msi_win_addr, sPAPRPHBState),
705
VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
706
vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
707
VMSTATE_STRUCT_ARRAY(msi_table, sPAPRPHBState, SPAPR_MSIX_MAX_DEVS, 0,
708
vmstate_spapr_pci_msi, struct spapr_pci_msi),
710
VMSTATE_END_OF_LIST()
714
static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
717
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
719
return sphb->dtbusname;
696
722
static void spapr_phb_class_init(ObjectClass *klass, void *data)
724
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
698
725
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
699
726
DeviceClass *dc = DEVICE_CLASS(klass);
728
hc->root_bus_path = spapr_phb_root_bus_path;
701
729
sdc->init = spapr_phb_init;
702
730
dc->props = spapr_phb_properties;
703
731
dc->reset = spapr_phb_reset;
732
dc->vmsd = &vmstate_spapr_pci;
706
735
static const TypeInfo spapr_phb_info = {