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From eb1251e345c20b9d6c55763e1e6fbed3ade40a2f Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Mon, 18 Feb 2013 16:58:34 +0000
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Subject: [PATCH 61/69] hw/nand: Support cache status bits and read cache
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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TODO: check vs spec, are we just ignoring these commands, is
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consider renaming the ready bits
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On reset, set the Ready bits in the status register (both the
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original bit 6 and the new bit 5 used by eg the STM NAND chips).
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Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
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[Riku Voipio: Fixes and restructuring patchset]
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Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
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[Peter Maydell: More fixes and cleanups for upstream submission]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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hw/block/nand.c | 14 +++++++++++---
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1 file changed, 11 insertions(+), 3 deletions(-)
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diff --git a/hw/block/nand.c b/hw/block/nand.c
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index 087ca14..d3bd470 100644
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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+# define NAND_CMD_READCACHESTART 0x31
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+# define NAND_CMD_READCACHEEXIT 0x34
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+# define NAND_CMD_READCACHELAST 0x3f
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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-# define NAND_IOSTATUS_READY (1 << 6)
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+# define NAND_IOSTATUS_READY (3 << 5)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define MAX_PAGE 0x800
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@@ -247,6 +250,7 @@ static void nand_command(NANDFlashState *s)
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+ case NAND_CMD_READCACHEEXIT:
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@@ -481,7 +485,10 @@ void nand_setio(DeviceState *dev, uint32_t value)
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NANDFlashState *s = (NANDFlashState *) dev;
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if (!s->ce && s->cle) {
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if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
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- if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
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+ if (s->cmd == NAND_CMD_READ0
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+ && (value == NAND_CMD_LPREAD2
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+ || value == NAND_CMD_READCACHESTART
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+ || value == NAND_CMD_READCACHELAST))
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if (value == NAND_CMD_RANDOMREAD1) {
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s->addr &= ~((1 << s->addr_shift) - 1);
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@@ -508,7 +515,8 @@ void nand_setio(DeviceState *dev, uint32_t value)
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s->cmd == NAND_CMD_BLOCKERASE2 ||
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s->cmd == NAND_CMD_NOSERIALREAD2 ||
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s->cmd == NAND_CMD_RANDOMREAD2 ||
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- s->cmd == NAND_CMD_RESET)
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+ s->cmd == NAND_CMD_RESET ||
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+ s->cmd == NAND_CMD_READCACHEEXIT)
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if (s->cmd != NAND_CMD_RANDOMREAD2) {