25
#if defined(__ARM_ARCH_7__) || \
26
defined(__ARM_ARCH_7A__) || \
27
defined(__ARM_ARCH_7EM__) || \
28
defined(__ARM_ARCH_7M__) || \
29
defined(__ARM_ARCH_7R__)
30
#define USE_ARMV7_INSTRUCTIONS
33
#if defined(USE_ARMV7_INSTRUCTIONS) || \
34
defined(__ARM_ARCH_6J__) || \
35
defined(__ARM_ARCH_6K__) || \
36
defined(__ARM_ARCH_6T2__) || \
37
defined(__ARM_ARCH_6Z__) || \
38
defined(__ARM_ARCH_6ZK__)
39
#define USE_ARMV6_INSTRUCTIONS
42
#if defined(USE_ARMV6_INSTRUCTIONS) || \
43
defined(__ARM_ARCH_5T__) || \
44
defined(__ARM_ARCH_5TE__) || \
45
defined(__ARM_ARCH_5TEJ__)
46
#define USE_ARMV5_INSTRUCTIONS
49
#ifdef USE_ARMV5_INSTRUCTIONS
50
static const int use_armv5_instructions = 1;
52
static const int use_armv5_instructions = 0;
54
#undef USE_ARMV5_INSTRUCTIONS
56
#ifdef USE_ARMV6_INSTRUCTIONS
57
static const int use_armv6_instructions = 1;
59
static const int use_armv6_instructions = 0;
61
#undef USE_ARMV6_INSTRUCTIONS
63
#ifdef USE_ARMV7_INSTRUCTIONS
64
static const int use_armv7_instructions = 1;
66
static const int use_armv7_instructions = 0;
68
#undef USE_ARMV7_INSTRUCTIONS
25
/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
27
# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
28
|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
29
|| defined(__ARM_ARCH_7EM__)
31
# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
32
|| defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
33
|| defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
35
# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
36
|| defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
37
|| defined(__ARM_ARCH_5TEJ__)
44
static int arm_arch = __ARM_ARCH;
46
#if defined(__ARM_ARCH_5T__) \
47
|| defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
48
# define use_armv5t_instructions 1
50
# define use_armv5t_instructions use_armv6_instructions
53
#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
54
#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
56
#ifndef use_idiv_instructions
57
bool use_idiv_instructions;
59
#ifdef CONFIG_GETAUXVAL
60
# include <sys/auxv.h>
71
64
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
1043
1036
static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
1045
if (use_armv5_instructions) {
1038
if (use_armv5t_instructions) {
1046
1039
tcg_out_blx(s, cond, arg);
1048
1041
tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
1926
1919
case INDEX_op_divu_i32:
1927
1920
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
1929
case INDEX_op_rem_i32:
1930
tcg_out_sdiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]);
1931
tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]);
1932
tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP,
1935
case INDEX_op_remu_i32:
1936
tcg_out_udiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]);
1937
tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]);
1938
tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP,
2042
2023
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2044
#if TCG_TARGET_HAS_div_i32
2045
2025
{ INDEX_op_div_i32, { "r", "r", "r" } },
2046
{ INDEX_op_rem_i32, { "r", "r", "r" } },
2047
2026
{ INDEX_op_divu_i32, { "r", "r", "r" } },
2048
{ INDEX_op_remu_i32, { "r", "r", "r" } },
2054
2031
static void tcg_target_init(TCGContext *s)
2056
#if !defined(CONFIG_USER_ONLY)
2058
if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
2033
#if defined(CONFIG_GETAUXVAL)
2034
/* Only probe for the platform and capabilities if we havn't already
2035
determined maximum values at compile time. */
2036
# if !defined(use_idiv_instructions)
2038
unsigned long hwcap = getauxval(AT_HWCAP);
2039
use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
2042
if (__ARM_ARCH < 7) {
2043
const char *pl = (const char *)getauxval(AT_PLATFORM);
2044
if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
2045
arm_arch = pl[1] - '0';
2048
#endif /* GETAUXVAL */
2062
2050
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
2063
2051
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2100
2088
tcg_out_movi32(s, COND_AL, ret, arg);
2091
/* Compute frame size via macros, to share between tcg_target_qemu_prologue
2092
and tcg_register_jit. */
2094
#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
2096
#define FRAME_SIZE \
2098
+ TCG_STATIC_CALL_ARGS_SIZE \
2099
+ CPU_TEMP_BUF_NLONGS * sizeof(long) \
2100
+ TCG_TARGET_STACK_ALIGN - 1) \
2101
& -TCG_TARGET_STACK_ALIGN)
2103
2103
static void tcg_target_qemu_prologue(TCGContext *s)
2107
2107
/* Calling convention requires us to save r4-r11 and lr. */
2108
2108
/* stmdb sp!, { r4 - r11, lr } */
2109
2109
tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
2111
/* Allocate the local stack frame. */
2112
frame_size = TCG_STATIC_CALL_ARGS_SIZE;
2113
frame_size += CPU_TEMP_BUF_NLONGS * sizeof(long);
2114
/* We saved an odd number of registers above; keep an 8 aligned stack. */
2115
frame_size = ((frame_size + TCG_TARGET_STACK_ALIGN - 1)
2116
& -TCG_TARGET_STACK_ALIGN) + 4;
2111
/* Reserve callee argument and tcg temp space. */
2112
stack_addend = FRAME_SIZE - PUSH_SIZE;
2118
2114
tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
2119
TCG_REG_CALL_STACK, frame_size, 1);
2115
TCG_REG_CALL_STACK, stack_addend, 1);
2120
2116
tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2121
2117
CPU_TEMP_BUF_NLONGS * sizeof(long));
2128
2124
/* Epilogue. We branch here via tb_ret_addr. */
2129
2125
tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
2130
TCG_REG_CALL_STACK, frame_size, 1);
2126
TCG_REG_CALL_STACK, stack_addend, 1);
2132
2128
/* ldmia sp!, { r4 - r11, pc } */
2133
2129
tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
2134
DebugFrameFDEHeader fde;
2135
uint8_t fde_def_cfa[4];
2136
uint8_t fde_reg_ofs[18];
2139
#define ELF_HOST_MACHINE EM_ARM
2141
/* We're expecting a 2 byte uleb128 encoded value. */
2142
QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2144
static DebugFrame debug_frame = {
2145
.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2148
.cie.code_align = 1,
2149
.cie.data_align = 0x7c, /* sleb128 -4 */
2150
.cie.return_column = 14,
2152
/* Total FDE size does not include the "len" member. */
2153
.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2156
12, 13, /* DW_CFA_def_cfa sp, ... */
2157
(FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2161
/* The following must match the stmdb in the prologue. */
2162
0x8e, 1, /* DW_CFA_offset, lr, -4 */
2163
0x8b, 2, /* DW_CFA_offset, r11, -8 */
2164
0x8a, 3, /* DW_CFA_offset, r10, -12 */
2165
0x89, 4, /* DW_CFA_offset, r9, -16 */
2166
0x88, 5, /* DW_CFA_offset, r8, -20 */
2167
0x87, 6, /* DW_CFA_offset, r7, -24 */
2168
0x86, 7, /* DW_CFA_offset, r6, -28 */
2169
0x85, 8, /* DW_CFA_offset, r5, -32 */
2170
0x84, 9, /* DW_CFA_offset, r4, -36 */
2174
void tcg_register_jit(void *buf, size_t buf_size)
2176
debug_frame.fde.func_start = (tcg_target_long) buf;
2177
debug_frame.fde.func_len = buf_size;
2179
tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));