161
static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
165
if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
166
fprintf(stderr, "Bad ram pointer %p\n", ptr);
161
172
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
163
174
ram_addr_t ram_addr;
176
187
void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
178
190
CPUArchState *env;
180
for (env = first_cpu; env != NULL; env = env->next_cpu) {
192
for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) {
183
196
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
248
261
target_ulong code_address;
249
262
uintptr_t addend;
264
hwaddr iotlb, xlat, sz;
253
266
assert(size >= TARGET_PAGE_SIZE);
254
267
if (size != TARGET_PAGE_SIZE) {
255
268
tlb_add_large_page(env, vaddr, size);
257
section = phys_page_find(address_space_memory.dispatch, paddr >> TARGET_PAGE_BITS);
272
section = address_space_translate_for_iotlb(&address_space_memory, paddr,
274
assert(sz >= TARGET_PAGE_SIZE);
258
276
#if defined(DEBUG_TLB)
259
277
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
260
" prot=%x idx=%d pd=0x%08lx\n",
261
vaddr, paddr, prot, mmu_idx, pd);
279
vaddr, paddr, prot, mmu_idx);
265
if (!(memory_region_is_ram(section->mr) ||
266
memory_region_is_romd(section->mr))) {
267
/* IO memory case (romd handled later) */
283
if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
268
285
address |= TLB_MMIO;
270
if (memory_region_is_ram(section->mr) ||
271
memory_region_is_romd(section->mr)) {
272
addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
273
+ memory_region_section_addr(section, paddr);
288
/* TLB_MMIO for rom/romd handled below */
289
addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
278
292
code_address = address;
279
iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,
293
iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat,
282
296
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
283
297
env->iotlb[mmu_idx][index] = iotlb - vaddr;
300
314
/* Write access calls the I/O callback. */
301
315
te->addr_write = address | TLB_MMIO;
302
316
} else if (memory_region_is_ram(section->mr)
303
&& !cpu_physical_memory_is_dirty(
304
section->mr->ram_addr
305
+ memory_region_section_addr(section, paddr))) {
317
&& !cpu_physical_memory_is_dirty(section->mr->ram_addr + xlat)) {
306
318
te->addr_write = address | TLB_NOTDIRTY;
308
320
te->addr_write = address;
332
344
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
333
345
mr = iotlb_to_region(pd);
334
346
if (memory_region_is_unassigned(mr)) {
335
#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
336
cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
338
cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
339
TARGET_FMT_lx "\n", addr);
347
CPUState *cpu = ENV_GET_CPU(env1);
348
CPUClass *cc = CPU_GET_CLASS(cpu);
350
if (cc->do_unassigned_access) {
351
cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
353
cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
354
TARGET_FMT_lx "\n", addr);
342
357
p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
343
358
return qemu_ram_addr_from_host_nofail(p);