2
* Nokia N-series internet tablets.
4
* Copyright (C) 2007 Nokia Corporation
5
* Written by Andrzej Zaborowski <andrew@openedhand.com>
7
* This program is free software; you can redistribute it and/or
8
* modify it under the terms of the GNU General Public License as
9
* published by the Free Software Foundation; either version 2 or
10
* (at your option) version 3 of the License.
12
* This program is distributed in the hope that it will be useful,
13
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
* GNU General Public License for more details.
17
* You should have received a copy of the GNU General Public License along
18
* with this program; if not, see <http://www.gnu.org/licenses/>.
21
#include "qemu-common.h"
22
#include "sysemu/sysemu.h"
23
#include "hw/arm/omap.h"
24
#include "hw/arm/arm.h"
26
#include "ui/console.h"
27
#include "hw/boards.h"
28
#include "hw/i2c/i2c.h"
29
#include "hw/devices.h"
30
#include "hw/block/flash.h"
34
#include "hw/loader.h"
35
#include "sysemu/blockdev.h"
36
#include "hw/sysbus.h"
37
#include "exec/address-spaces.h"
39
/* Nokia N8x0 support */
41
struct omap_mpu_state_s *mpu;
43
struct rfbi_chip_s blizzard;
57
#define N8X0_TUSB_ENABLE_GPIO 0
58
#define N800_MMC2_WP_GPIO 8
59
#define N800_UNKNOWN_GPIO0 9 /* out */
60
#define N810_MMC2_VIOSD_GPIO 9
61
#define N810_HEADSET_AMP_GPIO 10
62
#define N800_CAM_TURN_GPIO 12
63
#define N810_GPS_RESET_GPIO 12
64
#define N800_BLIZZARD_POWERDOWN_GPIO 15
65
#define N800_MMC1_WP_GPIO 23
66
#define N810_MMC2_VSD_GPIO 23
67
#define N8X0_ONENAND_GPIO 26
68
#define N810_BLIZZARD_RESET_GPIO 30
69
#define N800_UNKNOWN_GPIO2 53 /* out */
70
#define N8X0_TUSB_INT_GPIO 58
71
#define N8X0_BT_WKUP_GPIO 61
72
#define N8X0_STI_GPIO 62
73
#define N8X0_CBUS_SEL_GPIO 64
74
#define N8X0_CBUS_DAT_GPIO 65
75
#define N8X0_CBUS_CLK_GPIO 66
76
#define N8X0_WLAN_IRQ_GPIO 87
77
#define N8X0_BT_RESET_GPIO 92
78
#define N8X0_TEA5761_CS_GPIO 93
79
#define N800_UNKNOWN_GPIO 94
80
#define N810_TSC_RESET_GPIO 94
81
#define N800_CAM_ACT_GPIO 95
82
#define N810_GPS_WAKEUP_GPIO 95
83
#define N8X0_MMC_CS_GPIO 96
84
#define N8X0_WLAN_PWR_GPIO 97
85
#define N8X0_BT_HOST_WKUP_GPIO 98
86
#define N810_SPEAKER_AMP_GPIO 101
87
#define N810_KB_LOCK_GPIO 102
88
#define N800_TSC_TS_GPIO 103
89
#define N810_TSC_TS_GPIO 106
90
#define N8X0_HEADPHONE_GPIO 107
91
#define N8X0_RETU_GPIO 108
92
#define N800_TSC_KP_IRQ_GPIO 109
93
#define N810_KEYBOARD_GPIO 109
94
#define N800_BAT_COVER_GPIO 110
95
#define N810_SLIDE_GPIO 110
96
#define N8X0_TAHVO_GPIO 111
97
#define N800_UNKNOWN_GPIO4 112 /* out */
98
#define N810_SLEEPX_LED_GPIO 112
99
#define N800_TSC_RESET_GPIO 118 /* ? */
100
#define N810_AIC33_RESET_GPIO 118
101
#define N800_TSC_UNKNOWN_GPIO 119 /* out */
102
#define N8X0_TMP105_GPIO 125
106
#define XLDR_LL_UART 1
108
/* Addresses on the I2C bus 0 */
109
#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
110
#define N8X0_TCM825x_ADDR 0x29 /* Camera */
111
#define N810_LP5521_ADDR 0x32 /* LEDs */
112
#define N810_TSL2563_ADDR 0x3d /* Light sensor */
113
#define N810_LM8323_ADDR 0x45 /* Keyboard */
114
/* Addresses on the I2C bus 1 */
115
#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
116
#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
118
/* Chipselects on GPMC NOR interface */
119
#define N8X0_ONENAND_CS 0
120
#define N8X0_USB_ASYNC_CS 1
121
#define N8X0_USB_SYNC_CS 4
123
#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
125
static void n800_mmc_cs_cb(void *opaque, int line, int level)
127
/* TODO: this seems to actually be connected to the menelaus, to
128
* which also both MMC slots connect. */
129
omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
132
static void n8x0_gpio_setup(struct n800_s *s)
134
qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc, 1);
135
qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
137
qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
140
#define MAEMO_CAL_HEADER(...) \
141
'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
143
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
145
static const uint8_t n8x0_cal_wlan_mac[] = {
146
MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
147
0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
148
0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
149
0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
150
0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
151
0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
154
static const uint8_t n8x0_cal_bt_id[] = {
155
MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
156
0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
157
0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
161
static void n8x0_nand_setup(struct n800_s *s)
166
s->nand = qdev_create(NULL, "onenand");
167
qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
168
/* Either 0x40 or 0x48 are OK for the device ID */
169
qdev_prop_set_uint16(s->nand, "device_id", 0x48);
170
qdev_prop_set_uint16(s->nand, "version_id", 0);
171
qdev_prop_set_int32(s->nand, "shift", 1);
172
dinfo = drive_get(IF_MTD, 0, 0);
173
if (dinfo && dinfo->bdrv) {
174
qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
176
qdev_init_nofail(s->nand);
177
sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
178
qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
179
omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
180
sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
181
otp_region = onenand_raw_otp(s->nand);
183
memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
184
memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
185
/* XXX: in theory should also update the OOB for both pages */
188
static qemu_irq n8x0_system_powerdown;
190
static void n8x0_powerdown_req(Notifier *n, void *opaque)
192
qemu_irq_raise(n8x0_system_powerdown);
195
static Notifier n8x0_system_powerdown_notifier = {
196
.notify = n8x0_powerdown_req
199
static void n8x0_i2c_setup(struct n800_s *s)
202
qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
203
i2c_bus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
205
/* Attach a menelaus PM chip */
206
dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
207
qdev_connect_gpio_out(dev, 3,
208
qdev_get_gpio_in(s->mpu->ih[0],
209
OMAP_INT_24XX_SYS_NIRQ));
211
n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
212
qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
214
/* Attach a TMP105 PM chip (A0 wired to ground) */
215
dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
216
qdev_connect_gpio_out(dev, 0, tmp_irq);
219
/* Touchscreen and keypad controller */
220
static MouseTransformInfo n800_pointercal = {
223
.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
226
static MouseTransformInfo n810_pointercal = {
229
.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
232
#define RETU_KEYCODE 61 /* F3 */
234
static void n800_key_event(void *opaque, int keycode)
236
struct n800_s *s = (struct n800_s *) opaque;
237
int code = s->keymap[keycode & 0x7f];
240
if ((keycode & 0x7f) == RETU_KEYCODE)
241
retu_key_event(s->retu, !(keycode & 0x80));
245
tsc2301_key_event(s->tsc, code, !(keycode & 0x80));
248
static const int n800_keys[16] = {
262
64, /* FullScreen (F6) */
267
static void n800_tsc_kbd_setup(struct n800_s *s)
271
/* XXX: are the three pins inverted inside the chip between the
272
* tsc and the cpu (N4111)? */
273
s->tsc = spi_create_device(omap_mcspi_bus(s->mpu->mcspi, 0), "tsc2301", 0);
275
qdev_connect_gpio_out(s->tsc, 1, qdev_get_gpio_in(s->mpu->gpio,
276
N800_TSC_KP_IRQ_GPIO));
277
qdev_connect_gpio_out(s->tsc, 2, qdev_get_gpio_in(s->mpu->gpio,
280
for (i = 0; i < 0x80; i ++)
282
for (i = 0; i < 0x10; i ++)
283
if (n800_keys[i] >= 0)
284
s->keymap[n800_keys[i]] = i;
286
qemu_add_kbd_event_handler(n800_key_event, s);
288
tsc2301_set_transform(s->tsc, &n800_pointercal);
291
static void n810_tsc_setup(struct n800_s *s)
293
s->tsc = spi_create_device(omap_mcspi_bus(s->mpu->mcspi, 0), "tsc2005", 0);
294
qdev_connect_gpio_out(s->tsc, 0, qdev_get_gpio_in(s->mpu->gpio,
296
tsc2005_set_transform(s->tsc, &n810_pointercal, 400, 4000);
299
/* N810 Keyboard controller */
300
static void n810_key_event(void *opaque, int keycode)
302
struct n800_s *s = (struct n800_s *) opaque;
303
int code = s->keymap[keycode & 0x7f];
306
if ((keycode & 0x7f) == RETU_KEYCODE)
307
retu_key_event(s->retu, !(keycode & 0x80));
311
lm832x_key_event(s->kbd, code, !(keycode & 0x80));
316
static int n810_keys[0x80] = {
321
[0x05] = 14, /* Backspace */
331
[0x12] = 62, /* Menu (F4) */
333
[0x14] = 40, /* ' (Apostrophe) */
340
[0x1c] = 42, /* Shift (Left shift) */
341
[0x1f] = 65, /* Zoom+ (F7) */
344
[0x22] = 39, /* ; (Semicolon) */
345
[0x23] = 12, /* - (Minus) */
346
[0x24] = 13, /* = (Equal) */
347
[0x2b] = 56, /* Fn (Left Alt) */
349
[0x2f] = 66, /* Zoom- (F8) */
352
[0x32] = 29 | M, /* Right Ctrl */
353
[0x34] = 57, /* Space */
354
[0x35] = 51, /* , (Comma) */
355
[0x37] = 72 | M, /* Up */
356
[0x3c] = 82 | M, /* Compose (Insert) */
357
[0x3f] = 64, /* FullScreen (F6) */
360
[0x44] = 52, /* . (Dot) */
361
[0x46] = 77 | M, /* Right */
362
[0x4f] = 63, /* Home (F5) */
364
[0x53] = 80 | M, /* Down */
365
[0x55] = 28, /* Enter */
366
[0x5f] = 1, /* Cycle (ESC) */
369
[0x64] = 75 | M, /* Left */
373
[0x75] = 28 | M, /* KP Enter (KP Enter) */
375
[0x75] = 15, /* KP Enter (Tab) */
381
static void n810_kbd_setup(struct n800_s *s)
383
qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
386
for (i = 0; i < 0x80; i ++)
388
for (i = 0; i < 0x80; i ++)
389
if (n810_keys[i] > 0)
390
s->keymap[n810_keys[i]] = i;
392
qemu_add_kbd_event_handler(n810_key_event, s);
394
/* Attach the LM8322 keyboard to the I2C bus,
395
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
396
s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
397
"lm8323", N810_LM8323_ADDR);
398
qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
401
/* LCD MIPI DBI-C controller (URAL) */
423
static void mipid_reset(DeviceState *qdev)
425
struct mipid_s *s = FROM_SPI_DEVICE(struct mipid_s,
426
SPI_DEVICE_FROM_QDEV(qdev));
434
(1 << 7) | /* Register loading OK. */
435
(1 << 5) | /* The chip is attached. */
436
(1 << 4); /* Display glass still in one piece. */
446
static uint32_t mipid_txrx(SPIDevice *spidev, uint32_t cmd, int len)
448
struct mipid_s *s = FROM_SPI_DEVICE(struct mipid_s, spidev);
452
hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
454
if (s->p >= ARRAY_SIZE(s->resp))
457
ret = s->resp[s->p ++];
459
s->param[s->pm] = cmd;
467
case 0x01: /* SWRESET */
468
mipid_reset(&s->spi.qdev);
471
case 0x02: /* BSTROFF */
474
case 0x03: /* BSTRON */
478
case 0x04: /* RDDID */
480
s->resp[0] = (s->id >> 16) & 0xff;
481
s->resp[1] = (s->id >> 8) & 0xff;
482
s->resp[2] = (s->id >> 0) & 0xff;
485
case 0x06: /* RD_RED */
486
case 0x07: /* RD_GREEN */
487
/* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
488
* for the bootloader one needs to change this. */
489
case 0x08: /* RD_BLUE */
491
/* TODO: return first pixel components */
495
case 0x09: /* RDDST */
497
s->resp[0] = s->booster << 7;
498
s->resp[1] = (5 << 4) | (s->partial << 2) |
499
(s->sleep << 1) | s->normal;
500
s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
501
(s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
502
s->resp[3] = s->gamma << 6;
505
case 0x0a: /* RDDPM */
507
s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
508
(s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
510
case 0x0b: /* RDDMADCTR */
514
case 0x0c: /* RDDCOLMOD */
516
s->resp[0] = 5; /* 65K colours */
518
case 0x0d: /* RDDIM */
520
s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
522
case 0x0e: /* RDDSM */
524
s->resp[0] = s->te << 7;
526
case 0x0f: /* RDDSDR */
528
s->resp[0] = s->selfcheck;
531
case 0x10: /* SLPIN */
534
case 0x11: /* SLPOUT */
536
s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
539
case 0x12: /* PTLON */
544
case 0x13: /* NORON */
550
case 0x20: /* INVOFF */
553
case 0x21: /* INVON */
557
case 0x22: /* APOFF */
558
case 0x23: /* APON */
561
case 0x25: /* WRCNTR */
566
case 0x26: /* GAMSET */
568
s->gamma = ffs(s->param[0] & 0xf) - 1;
573
case 0x28: /* DISPOFF */
576
case 0x29: /* DISPON */
580
case 0x2a: /* CASET */
581
case 0x2b: /* RASET */
582
case 0x2c: /* RAMWR */
583
case 0x2d: /* RGBSET */
584
case 0x2e: /* RAMRD */
585
case 0x30: /* PTLAR */
586
case 0x33: /* SCRLAR */
589
case 0x34: /* TEOFF */
592
case 0x35: /* TEON */
599
case 0x36: /* MADCTR */
602
case 0x37: /* VSCSAD */
608
case 0x38: /* IDMOFF */
609
case 0x39: /* IDMON */
610
case 0x3a: /* COLMOD */
613
case 0xb0: /* CLKINT / DISCTL */
614
case 0xb1: /* CLKEXT */
619
case 0xb4: /* FRMSEL */
622
case 0xb5: /* FRM8SEL */
623
case 0xb6: /* TMPRNG / INIESC */
624
case 0xb7: /* TMPHIS / NOP2 */
625
case 0xb8: /* TMPREAD / MADCTL */
626
case 0xba: /* DISTCTR */
627
case 0xbb: /* EPVOL */
630
case 0xbd: /* Unknown */
636
case 0xc2: /* IFMOD */
641
case 0xc6: /* PWRCTL */
642
case 0xc7: /* PPWRCTL */
643
case 0xd0: /* EPWROUT */
644
case 0xd1: /* EPWRIN */
645
case 0xd4: /* RDEV */
646
case 0xd5: /* RDRR */
649
case 0xda: /* RDID1 */
651
s->resp[0] = (s->id >> 16) & 0xff;
653
case 0xdb: /* RDID2 */
655
s->resp[0] = (s->id >> 8) & 0xff;
657
case 0xdc: /* RDID3 */
659
s->resp[0] = (s->id >> 0) & 0xff;
664
qemu_log_mask(LOG_GUEST_ERROR,
665
"%s: unknown command %02x\n", __func__, s->cmd);
672
static int mipid_init(SPIDevice *spidev)
677
static Property mipid_properties[] = {
678
DEFINE_PROP_UINT32("id", struct mipid_s, id, 0),
679
DEFINE_PROP_END_OF_LIST()
682
static void mipid_class_init(ObjectClass *klass, void *data)
684
DeviceClass *dc = DEVICE_CLASS(klass);
685
SPIDeviceClass *k = SPI_DEVICE_CLASS(klass);
687
k->init = mipid_init;
688
k->txrx = mipid_txrx;
689
dc->reset = mipid_reset;
690
dc->props = mipid_properties;
693
static TypeInfo mipid_info = {
695
.parent = TYPE_SPI_DEVICE,
696
.instance_size = sizeof(struct mipid_s),
697
.class_init = mipid_class_init,
700
static void n8x0_spi_setup(struct n800_s *s)
702
s->mipid = spi_create_device_noinit(omap_mcspi_bus(s->mpu->mcspi, 0),
704
qdev_prop_set_uint32(s->mipid, "id", 0x838f03);
705
qdev_init_nofail(s->mipid);
708
/* This task is normally performed by the bootloader. If we're loading
709
* a kernel directly, we need to enable the Blizzard ourselves. */
710
static void n800_dss_init(struct rfbi_chip_s *chip)
714
chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
715
chip->write(chip->opaque, 1, 0x64);
716
chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
717
chip->write(chip->opaque, 1, 0x1e);
718
chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
719
chip->write(chip->opaque, 1, 0xe0);
720
chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
721
chip->write(chip->opaque, 1, 0x01);
722
chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
723
chip->write(chip->opaque, 1, 0x06);
724
chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
725
chip->write(chip->opaque, 1, 1); /* Enable bit */
727
chip->write(chip->opaque, 0, 0x6c);
728
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
729
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
730
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
731
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
732
chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
733
chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
734
chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
735
chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
736
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
737
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
738
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
739
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
740
chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
741
chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
742
chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
743
chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
744
chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
745
chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
747
fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
748
/* Display Memory Data Port */
749
chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
753
static void n8x0_dss_setup(struct n800_s *s)
755
s->blizzard.opaque = s1d13745_init(NULL);
756
s->blizzard.block = s1d13745_write_block;
757
s->blizzard.write = s1d13745_write;
758
s->blizzard.read = s1d13745_read;
760
omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
763
static void n8x0_cbus_setup(struct n800_s *s)
765
qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
766
qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
767
qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
769
CBus *cbus = cbus_init(dat_out);
771
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
772
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
773
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
775
cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
776
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
779
static void n8x0_uart_setup(struct n800_s *s)
781
CharDriverState *radio = uart_hci_init(
782
qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
784
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
785
csrhci_pins_get(radio)[csrhci_pin_reset]);
786
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
787
csrhci_pins_get(radio)[csrhci_pin_wakeup]);
789
omap_uart_attach(s->mpu->uart[BT_UART], radio, "bt-uart");
792
static void n8x0_usb_setup(struct n800_s *s)
795
s->usb = qdev_create(NULL, "tusb6010");
796
dev = SYS_BUS_DEVICE(s->usb);
797
qdev_init_nofail(s->usb);
798
sysbus_connect_irq(dev, 0,
799
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
800
/* Using the NOR interface */
801
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
802
sysbus_mmio_get_region(dev, 0));
803
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
804
sysbus_mmio_get_region(dev, 1));
805
qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
806
qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
809
/* Setup done before the main bootloader starts by some early setup code
810
* - used when we want to run the main bootloader in emulation. This
811
* isn't documented. */
812
static uint32_t n800_pinout[104] = {
813
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
814
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
815
0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
816
0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
817
0x01241800, 0x18181818, 0x000000f0, 0x01300000,
818
0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
819
0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
820
0x007c0000, 0x00000000, 0x00000088, 0x00840000,
821
0x00000000, 0x00000094, 0x00980300, 0x0f180003,
822
0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
823
0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
824
0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
825
0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
826
0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
827
0x00000000, 0x00000038, 0x00340000, 0x00000000,
828
0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
829
0x005c0808, 0x08080808, 0x08080058, 0x00540808,
830
0x08080808, 0x0808006c, 0x00680808, 0x08080808,
831
0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
832
0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
833
0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
834
0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
835
0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
836
0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
837
0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
838
0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
841
static void n800_setup_nolo_tags(void *sram_base)
844
uint32_t *p = sram_base + 0x8000;
845
uint32_t *v = sram_base + 0xa000;
847
memset(p, 0, 0x3000);
849
strcpy((void *) (p + 0), "QEMU N800");
851
strcpy((void *) (p + 8), "F5");
853
stl_raw(p + 10, 0x04f70000);
854
strcpy((void *) (p + 9), "RX-34");
856
/* RAM size in MB? */
857
stl_raw(p + 12, 0x80);
859
/* Pointer to the list of tags */
860
stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
862
/* The NOLO tags start here */
863
p = sram_base + 0x9000;
864
#define ADD_TAG(tag, len) \
865
stw_raw((uint16_t *) p + 0, tag); \
866
stw_raw((uint16_t *) p + 1, len); p ++; \
867
stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
869
/* OMAP STI console? Pin out settings? */
870
ADD_TAG(0x6e01, 414);
871
for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
872
stl_raw(v ++, n800_pinout[i]);
874
/* Kernel memsize? */
878
/* NOLO serial console */
880
stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
883
/* CBUS settings (Retu/AVilma) */
885
stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
886
stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
887
stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
891
/* Nokia ASIC BB5 (Retu/Tahvo) */
893
stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
894
stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
899
stw_raw((uint16_t *) v + 0, 30); /* ??? */
900
stw_raw((uint16_t *) v + 1, 24); /* ??? */
906
stw_raw((uint16_t *) (v ++), 15); /* ??? */
909
/* I^2C (Menelaus) */
911
stl_raw(v ++, 0x00720000); /* ??? */
915
stw_raw((uint16_t *) v + 0, 94); /* ??? */
916
stw_raw((uint16_t *) v + 1, 23); /* ??? */
917
stw_raw((uint16_t *) v + 2, 0); /* ??? */
920
/* OMAP gpio switch info */
922
strcpy((void *) v, "bat_cover"); v += 3;
923
stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
924
stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
926
strcpy((void *) v, "cam_act"); v += 3;
927
stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
928
stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
930
strcpy((void *) v, "cam_turn"); v += 3;
931
stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
932
stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
934
strcpy((void *) v, "headphone"); v += 3;
935
stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
936
stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
941
stl_raw(v ++, 0x5c623d01); /* ??? */
942
stl_raw(v ++, 0x00000201); /* ??? */
943
stl_raw(v ++, 0x00000000); /* ??? */
945
/* CX3110x WLAN settings */
947
stl_raw(v ++, 0x00610025); /* ??? */
948
stl_raw(v ++, 0xffff0057); /* ??? */
950
/* MMC host settings */
952
stl_raw(v ++, 0xffff000f); /* ??? */
953
stl_raw(v ++, 0xffffffff); /* ??? */
954
stl_raw(v ++, 0x00000060); /* ??? */
956
/* OneNAND chip select */
958
stl_raw(v ++, 0x00000401); /* ??? */
959
stl_raw(v ++, 0x0002003a); /* ??? */
960
stl_raw(v ++, 0x00000002); /* ??? */
962
/* TEA5761 sensor settings */
964
stl_raw(v ++, 93); /* GPIO num ??? */
970
/* Kernel UART / console */
974
/* End of the list */
975
stl_raw(p ++, 0x00000000);
976
stl_raw(p ++, 0x00000000);
979
/* This task is normally performed by the bootloader. If we're loading
980
* a kernel directly, we need to set up GPMC mappings ourselves. */
981
static void n800_gpmc_init(struct n800_s *s)
984
(0xf << 8) | /* MASKADDRESS */
985
(1 << 6) | /* CSVALID */
986
(4 << 0); /* BASEADDRESS */
988
cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
989
&config7, sizeof(config7));
992
/* Setup sequence done by the bootloader */
993
static void n8x0_boot_init(void *opaque)
995
struct n800_s *s = (struct n800_s *) opaque;
999
#define omap_writel(addr, val) \
1001
cpu_physical_memory_write(addr, &buf, sizeof(buf))
1003
omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
1004
omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
1005
omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
1006
omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
1007
omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
1008
omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
1009
omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1010
omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1011
omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1012
omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1013
omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1014
omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1015
omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1016
omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1017
omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1018
omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1019
omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1020
omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1021
omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1022
omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1023
omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1024
omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1025
omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1026
omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1027
omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1028
omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1029
omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1030
omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1031
omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1032
omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1033
omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1034
omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1035
omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1036
omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1037
omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1038
(0x78 << 12) | (6 << 8));
1039
omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1045
n800_dss_init(&s->blizzard);
1048
s->mpu->cpu->env.GE = 0x5;
1050
/* If the machine has a slided keyboard, open it */
1052
qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1055
#define OMAP_TAG_NOKIA_BT 0x4e01
1056
#define OMAP_TAG_WLAN_CX3110X 0x4e02
1057
#define OMAP_TAG_CBUS 0x4e03
1058
#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1060
static struct omap_gpiosw_info_s {
1064
} n800_gpiosw_info[] = {
1066
"bat_cover", N800_BAT_COVER_GPIO,
1067
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1069
"cam_act", N800_CAM_ACT_GPIO,
1070
OMAP_GPIOSW_TYPE_ACTIVITY,
1072
"cam_turn", N800_CAM_TURN_GPIO,
1073
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1075
"headphone", N8X0_HEADPHONE_GPIO,
1076
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1079
}, n810_gpiosw_info[] = {
1081
"gps_reset", N810_GPS_RESET_GPIO,
1082
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1084
"gps_wakeup", N810_GPS_WAKEUP_GPIO,
1085
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1087
"headphone", N8X0_HEADPHONE_GPIO,
1088
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1090
"kb_lock", N810_KB_LOCK_GPIO,
1091
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1093
"sleepx_led", N810_SLEEPX_LED_GPIO,
1094
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1096
"slide", N810_SLIDE_GPIO,
1097
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1102
static struct omap_partition_info_s {
1107
} n800_part_info[] = {
1108
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
1109
{ 0x00020000, 0x00060000, 0x0, "config" },
1110
{ 0x00080000, 0x00200000, 0x0, "kernel" },
1111
{ 0x00280000, 0x00200000, 0x3, "initfs" },
1112
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1115
}, n810_part_info[] = {
1116
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
1117
{ 0x00020000, 0x00060000, 0x0, "config" },
1118
{ 0x00080000, 0x00220000, 0x0, "kernel" },
1119
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
1120
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1125
static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1127
static int n8x0_atag_setup(void *p, int model)
1132
struct omap_gpiosw_info_s *gpiosw;
1133
struct omap_partition_info_s *partition;
1138
stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1139
stw_raw(w ++, 4); /* u16 len */
1140
stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1144
stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1145
stw_raw(w ++, 4); /* u16 len */
1146
stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1147
stw_raw(w ++, 115200); /* u32 console_speed */
1150
stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1151
stw_raw(w ++, 36); /* u16 len */
1152
strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1154
strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1156
stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1157
stw_raw(w ++, 24); /* u8 data_lines */
1159
stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1160
stw_raw(w ++, 8); /* u16 len */
1161
stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1162
stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1163
stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1166
stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1167
stw_raw(w ++, 4); /* u16 len */
1168
stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1169
stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1171
gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1172
for (; gpiosw->name; gpiosw ++) {
1173
stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1174
stw_raw(w ++, 20); /* u16 len */
1175
strcpy((void *) w, gpiosw->name); /* char name[12] */
1177
stw_raw(w ++, gpiosw->line); /* u16 gpio */
1178
stw_raw(w ++, gpiosw->type);
1183
stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1184
stw_raw(w ++, 12); /* u16 len */
1186
stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1187
stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1188
stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1189
stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1190
stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1191
memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1193
stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1196
stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1197
stw_raw(w ++, 8); /* u16 len */
1198
stw_raw(w ++, 0x25); /* u8 chip_type */
1199
stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1200
stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1201
stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1203
stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1204
stw_raw(w ++, 16); /* u16 len */
1206
stw_raw(w ++, 0x23f); /* unsigned flags */
1207
stw_raw(w ++, -1); /* s16 power_pin */
1208
stw_raw(w ++, -1); /* s16 switch_pin */
1209
stw_raw(w ++, -1); /* s16 wp_pin */
1210
stw_raw(w ++, 0x240); /* unsigned flags */
1211
stw_raw(w ++, 0xc000); /* s16 power_pin */
1212
stw_raw(w ++, 0x0248); /* s16 switch_pin */
1213
stw_raw(w ++, 0xc000); /* s16 wp_pin */
1215
stw_raw(w ++, 0xf); /* unsigned flags */
1216
stw_raw(w ++, -1); /* s16 power_pin */
1217
stw_raw(w ++, -1); /* s16 switch_pin */
1218
stw_raw(w ++, -1); /* s16 wp_pin */
1219
stw_raw(w ++, 0); /* unsigned flags */
1220
stw_raw(w ++, 0); /* s16 power_pin */
1221
stw_raw(w ++, 0); /* s16 switch_pin */
1222
stw_raw(w ++, 0); /* s16 wp_pin */
1225
stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1226
stw_raw(w ++, 4); /* u16 len */
1227
stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1230
partition = (model == 810) ? n810_part_info : n800_part_info;
1231
for (; partition->name; partition ++) {
1232
stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1233
stw_raw(w ++, 28); /* u16 len */
1234
strcpy((void *) w, partition->name); /* char name[16] */
1235
l = (void *) (w + 8);
1236
stl_raw(l ++, partition->size); /* unsigned int size */
1237
stl_raw(l ++, partition->offset); /* unsigned int offset */
1238
stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1242
stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1243
stw_raw(w ++, 12); /* u16 len */
1245
strcpy((void *) w, "por"); /* char reason_str[12] */
1246
strcpy((void *) w, "charger"); /* char reason_str[12] */
1247
strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1248
strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1249
strcpy((void *) w, "mbus"); /* char reason_str[12] */
1250
strcpy((void *) w, "unknown"); /* char reason_str[12] */
1251
strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1252
strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1253
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1254
strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1256
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1260
tag = (model == 810) ? "RX-44" : "RX-34";
1261
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1262
stw_raw(w ++, 24); /* u16 len */
1263
strcpy((void *) w, "product"); /* char component[12] */
1265
strcpy((void *) w, tag); /* char version[12] */
1268
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1269
stw_raw(w ++, 24); /* u16 len */
1270
strcpy((void *) w, "hw-build"); /* char component[12] */
1272
strcpy((void *) w, "QEMU ");
1273
pstrcat((void *) w, 12, qemu_get_version()); /* char version[12] */
1276
tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1277
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1278
stw_raw(w ++, 24); /* u16 len */
1279
strcpy((void *) w, "nolo"); /* char component[12] */
1281
strcpy((void *) w, tag); /* char version[12] */
1284
return (void *) w - p;
1287
static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1289
return n8x0_atag_setup(p, 800);
1292
static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1294
return n8x0_atag_setup(p, 810);
1297
static void n8x0_init(QEMUMachineInitArgs *args,
1298
struct arm_boot_info *binfo, int model)
1300
MemoryRegion *sysmem = get_system_memory();
1301
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1302
int sdram_size = binfo->ram_size;
1304
s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model);
1306
/* Setup peripherals
1308
* Believed external peripherals layout in the N810:
1313
* Conexant cx3110x (WLAN)
1314
* optional: pc2400m (WiMAX)
1316
* TLV320AIC33 (audio codec)
1317
* TCM825x (camera by Toshiba)
1318
* lp5521 (clever LEDs)
1319
* tsl2563 (light sensor, hwmon, model 7, rev. 0)
1320
* lm8323 (keypad, manf 00, rev 04)
1322
* tmp105 (temperature sensor, hwmon)
1324
* (somewhere on i2c - maybe N800-only)
1325
* tea5761 (FM tuner)
1328
* (some serial port)
1329
* csr41814 (Bluetooth)
1335
n800_tsc_kbd_setup(s);
1336
else if (model == 810) {
1344
if (usb_enabled(false)) {
1348
if (args->kernel_filename) {
1349
/* Or at the linux loader. */
1350
binfo->kernel_filename = args->kernel_filename;
1351
binfo->kernel_cmdline = args->kernel_cmdline;
1352
binfo->initrd_filename = args->initrd_filename;
1353
arm_load_kernel(s->mpu->cpu, binfo);
1355
qemu_register_reset(n8x0_boot_init, s);
1358
if (option_rom[0].name &&
1359
(args->boot_device[0] == 'n' || !args->kernel_filename)) {
1360
uint8_t nolo_tags[0x10000];
1361
/* No, wait, better start at the ROM. */
1362
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1364
/* This is intended for loading the `secondary.bin' program from
1365
* Nokia images (the NOLO bootloader). The entry point seems
1366
* to be at OMAP2_Q2_BASE + 0x400000.
1368
* The `2nd.bin' files contain some kind of earlier boot code and
1369
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
1371
* The code above is for loading the `zImage' file from Nokia
1373
load_image_targphys(option_rom[0].name,
1374
OMAP2_Q2_BASE + 0x400000,
1375
sdram_size - 0x400000);
1377
n800_setup_nolo_tags(nolo_tags);
1378
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1382
static struct arm_boot_info n800_binfo = {
1383
.loader_start = OMAP2_Q2_BASE,
1384
/* Actually two chips of 0x4000000 bytes each */
1385
.ram_size = 0x08000000,
1387
.atag_board = n800_atag_setup,
1390
static struct arm_boot_info n810_binfo = {
1391
.loader_start = OMAP2_Q2_BASE,
1392
/* Actually two chips of 0x4000000 bytes each */
1393
.ram_size = 0x08000000,
1394
/* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1395
* used by some older versions of the bootloader and 5555 is used
1396
* instead (including versions that shipped with many devices). */
1398
.atag_board = n810_atag_setup,
1401
static void n800_init(QEMUMachineInitArgs *args)
1403
return n8x0_init(args, &n800_binfo, 800);
1406
static void n810_init(QEMUMachineInitArgs *args)
1408
return n8x0_init(args, &n810_binfo, 810);
1411
static QEMUMachine n800_machine = {
1413
.desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1415
DEFAULT_MACHINE_OPTIONS,
1418
static QEMUMachine n810_machine = {
1420
.desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1422
DEFAULT_MACHINE_OPTIONS,
1425
static void nseries_register_types(void)
1427
type_register_static(&mipid_info);
1430
static void nseries_machine_init(void)
1432
qemu_register_machine(&n800_machine);
1433
qemu_register_machine(&n810_machine);
1436
type_init(nseries_register_types);
1437
machine_init(nseries_machine_init);