57
57
static int xio3130_downstream_initfn(PCIDevice *d)
59
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
60
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
61
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
59
PCIEPort *p = PCIE_PORT(d);
60
PCIESlot *s = PCIE_SLOT(d);
64
63
rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
114
113
static void xio3130_downstream_exitfn(PCIDevice *d)
116
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
117
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
118
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
115
PCIESlot *s = PCIE_SLOT(d);
120
117
pcie_aer_exit(d);
121
118
pcie_chassis_del_slot(s);
141
br = DO_UPCAST(PCIBridge, dev, d);
143
qdev = &br->dev.qdev;
144
141
pci_bridge_map_irq(br, bus_name, map_irq);
145
142
qdev_prop_set_uint8(qdev, "port", port);
146
143
qdev_prop_set_uint8(qdev, "chassis", chassis);
147
144
qdev_prop_set_uint16(qdev, "slot", slot);
148
145
qdev_init_nofail(qdev);
150
return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
153
150
static const VMStateDescription vmstate_xio3130_downstream = {
157
154
.minimum_version_id_old = 1,
158
155
.post_load = pcie_cap_slot_post_load,
159
156
.fields = (VMStateField[]) {
160
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
161
VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
162
vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
158
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
159
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
163
160
VMSTATE_END_OF_LIST()
167
static Property xio3130_downstream_properties[] = {
168
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
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DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
170
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
171
DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
172
port.br.dev.exp.aer_log.log_max,
173
PCIE_AER_LOG_MAX_DEFAULT),
174
DEFINE_PROP_END_OF_LIST(),
177
164
static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
179
166
DeviceClass *dc = DEVICE_CLASS(klass);
187
174
k->vendor_id = PCI_VENDOR_ID_TI;
188
175
k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
189
176
k->revision = XIO3130_REVISION;
177
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
190
178
dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
191
179
dc->reset = xio3130_downstream_reset;
192
180
dc->vmsd = &vmstate_xio3130_downstream;
193
dc->props = xio3130_downstream_properties;
196
183
static const TypeInfo xio3130_downstream_info = {
197
184
.name = "xio3130-downstream",
198
.parent = TYPE_PCI_DEVICE,
199
.instance_size = sizeof(PCIESlot),
185
.parent = TYPE_PCIE_SLOT,
200
186
.class_init = xio3130_downstream_class_init,