2
* Nokia N-series internet tablets.
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* Copyright (C) 2007 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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#include "qemu-common.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/omap.h"
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#include "hw/arm/arm.h"
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#include "ui/console.h"
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#include "hw/boards.h"
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#include "hw/i2c/i2c.h"
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#include "hw/devices.h"
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#include "hw/block/flash.h"
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#include "hw/loader.h"
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#include "sysemu/blockdev.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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/* Nokia N8x0 support */
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struct omap_mpu_state_s *mpu;
42
struct rfbi_chip_s blizzard;
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uint32_t (*txrx)(void *opaque, uint32_t value, int len);
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#define N8X0_TUSB_ENABLE_GPIO 0
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#define N800_MMC2_WP_GPIO 8
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#define N800_UNKNOWN_GPIO0 9 /* out */
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#define N810_MMC2_VIOSD_GPIO 9
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#define N810_HEADSET_AMP_GPIO 10
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#define N800_CAM_TURN_GPIO 12
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#define N810_GPS_RESET_GPIO 12
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#define N800_BLIZZARD_POWERDOWN_GPIO 15
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#define N800_MMC1_WP_GPIO 23
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#define N810_MMC2_VSD_GPIO 23
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#define N8X0_ONENAND_GPIO 26
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#define N810_BLIZZARD_RESET_GPIO 30
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#define N800_UNKNOWN_GPIO2 53 /* out */
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#define N8X0_TUSB_INT_GPIO 58
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#define N8X0_BT_WKUP_GPIO 61
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#define N8X0_STI_GPIO 62
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#define N8X0_CBUS_SEL_GPIO 64
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#define N8X0_CBUS_DAT_GPIO 65
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#define N8X0_CBUS_CLK_GPIO 66
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#define N8X0_WLAN_IRQ_GPIO 87
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#define N8X0_BT_RESET_GPIO 92
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#define N8X0_TEA5761_CS_GPIO 93
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#define N800_UNKNOWN_GPIO 94
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#define N810_TSC_RESET_GPIO 94
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#define N800_CAM_ACT_GPIO 95
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#define N810_GPS_WAKEUP_GPIO 95
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#define N8X0_MMC_CS_GPIO 96
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#define N8X0_WLAN_PWR_GPIO 97
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#define N8X0_BT_HOST_WKUP_GPIO 98
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#define N810_SPEAKER_AMP_GPIO 101
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#define N810_KB_LOCK_GPIO 102
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#define N800_TSC_TS_GPIO 103
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#define N810_TSC_TS_GPIO 106
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#define N8X0_HEADPHONE_GPIO 107
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#define N8X0_RETU_GPIO 108
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#define N800_TSC_KP_IRQ_GPIO 109
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#define N810_KEYBOARD_GPIO 109
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#define N800_BAT_COVER_GPIO 110
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#define N810_SLIDE_GPIO 110
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#define N8X0_TAHVO_GPIO 111
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#define N800_UNKNOWN_GPIO4 112 /* out */
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#define N810_SLEEPX_LED_GPIO 112
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#define N800_TSC_RESET_GPIO 118 /* ? */
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#define N810_AIC33_RESET_GPIO 118
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#define N800_TSC_UNKNOWN_GPIO 119 /* out */
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#define N8X0_TMP105_GPIO 125
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#define XLDR_LL_UART 1
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/* Addresses on the I2C bus 0 */
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#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
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#define N8X0_TCM825x_ADDR 0x29 /* Camera */
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#define N810_LP5521_ADDR 0x32 /* LEDs */
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#define N810_TSL2563_ADDR 0x3d /* Light sensor */
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#define N810_LM8323_ADDR 0x45 /* Keyboard */
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/* Addresses on the I2C bus 1 */
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#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
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#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
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/* Chipselects on GPMC NOR interface */
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#define N8X0_ONENAND_CS 0
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#define N8X0_USB_ASYNC_CS 1
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#define N8X0_USB_SYNC_CS 4
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#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
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static void n800_mmc_cs_cb(void *opaque, int line, int level)
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/* TODO: this seems to actually be connected to the menelaus, to
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* which also both MMC slots connect. */
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omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
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static void n8x0_gpio_setup(struct n800_s *s)
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qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc, 1);
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qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
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qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
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#define MAEMO_CAL_HEADER(...) \
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'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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static const uint8_t n8x0_cal_wlan_mac[] = {
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MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
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0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
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0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
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0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
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0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
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static const uint8_t n8x0_cal_bt_id[] = {
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MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
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0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
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0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
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static void n8x0_nand_setup(struct n800_s *s)
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s->nand = qdev_create(NULL, "onenand");
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qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
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/* Either 0x40 or 0x48 are OK for the device ID */
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qdev_prop_set_uint16(s->nand, "device_id", 0x48);
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qdev_prop_set_uint16(s->nand, "version_id", 0);
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qdev_prop_set_int32(s->nand, "shift", 1);
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dinfo = drive_get(IF_MTD, 0, 0);
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if (dinfo && dinfo->bdrv) {
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qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
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qdev_init_nofail(s->nand);
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sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
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qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
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omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
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otp_region = onenand_raw_otp(s->nand);
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memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
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memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
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/* XXX: in theory should also update the OOB for both pages */
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static qemu_irq n8x0_system_powerdown;
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static void n8x0_powerdown_req(Notifier *n, void *opaque)
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qemu_irq_raise(n8x0_system_powerdown);
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static Notifier n8x0_system_powerdown_notifier = {
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.notify = n8x0_powerdown_req
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static void n8x0_i2c_setup(struct n800_s *s)
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qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
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i2c_bus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
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/* Attach a menelaus PM chip */
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dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
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qdev_connect_gpio_out(dev, 3,
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qdev_get_gpio_in(s->mpu->ih[0],
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OMAP_INT_24XX_SYS_NIRQ));
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n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
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qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
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/* Attach a TMP105 PM chip (A0 wired to ground) */
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dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
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qdev_connect_gpio_out(dev, 0, tmp_irq);
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/* Touchscreen and keypad controller */
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static MouseTransformInfo n800_pointercal = {
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.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
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static MouseTransformInfo n810_pointercal = {
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.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
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#define RETU_KEYCODE 61 /* F3 */
236
static void n800_key_event(void *opaque, int keycode)
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struct n800_s *s = (struct n800_s *) opaque;
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int code = s->keymap[keycode & 0x7f];
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if ((keycode & 0x7f) == RETU_KEYCODE)
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retu_key_event(s->retu, !(keycode & 0x80));
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tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
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static const int n800_keys[16] = {
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64, /* FullScreen (F6) */
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static void n800_tsc_kbd_setup(struct n800_s *s)
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/* XXX: are the three pins inverted inside the chip between the
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* tsc and the cpu (N4111)? */
275
qemu_irq penirq = NULL; /* NC */
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qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
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qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
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s->ts.chip = tsc2301_init(penirq, kbirq, dav);
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s->ts.opaque = s->ts.chip->opaque;
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s->ts.txrx = tsc210x_txrx;
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for (i = 0; i < 0x80; i ++)
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for (i = 0; i < 0x10; i ++)
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if (n800_keys[i] >= 0)
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s->keymap[n800_keys[i]] = i;
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qemu_add_kbd_event_handler(n800_key_event, s);
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tsc210x_set_transform(s->ts.chip, &n800_pointercal);
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static void n810_tsc_setup(struct n800_s *s)
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qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
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s->ts.opaque = tsc2005_init(pintdav);
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s->ts.txrx = tsc2005_txrx;
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tsc2005_set_transform(s->ts.opaque, &n810_pointercal, 400, 4000);
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/* N810 Keyboard controller */
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static void n810_key_event(void *opaque, int keycode)
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struct n800_s *s = (struct n800_s *) opaque;
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int code = s->keymap[keycode & 0x7f];
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if ((keycode & 0x7f) == RETU_KEYCODE)
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retu_key_event(s->retu, !(keycode & 0x80));
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lm832x_key_event(s->kbd, code, !(keycode & 0x80));
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static int n810_keys[0x80] = {
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[0x05] = 14, /* Backspace */
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[0x12] = 62, /* Menu (F4) */
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[0x14] = 40, /* ' (Apostrophe) */
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[0x1c] = 42, /* Shift (Left shift) */
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[0x1f] = 65, /* Zoom+ (F7) */
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[0x22] = 39, /* ; (Semicolon) */
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[0x23] = 12, /* - (Minus) */
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[0x24] = 13, /* = (Equal) */
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[0x2b] = 56, /* Fn (Left Alt) */
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[0x2f] = 66, /* Zoom- (F8) */
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[0x32] = 29 | M, /* Right Ctrl */
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[0x34] = 57, /* Space */
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[0x35] = 51, /* , (Comma) */
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[0x37] = 72 | M, /* Up */
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[0x3c] = 82 | M, /* Compose (Insert) */
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[0x3f] = 64, /* FullScreen (F6) */
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[0x44] = 52, /* . (Dot) */
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[0x46] = 77 | M, /* Right */
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[0x4f] = 63, /* Home (F5) */
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[0x53] = 80 | M, /* Down */
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[0x55] = 28, /* Enter */
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[0x5f] = 1, /* Cycle (ESC) */
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[0x64] = 75 | M, /* Left */
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[0x75] = 28 | M, /* KP Enter (KP Enter) */
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[0x75] = 15, /* KP Enter (Tab) */
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static void n810_kbd_setup(struct n800_s *s)
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qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
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for (i = 0; i < 0x80; i ++)
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for (i = 0; i < 0x80; i ++)
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if (n810_keys[i] > 0)
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s->keymap[n810_keys[i]] = i;
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qemu_add_kbd_event_handler(n810_key_event, s);
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/* Attach the LM8322 keyboard to the I2C bus,
400
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
401
s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
402
"lm8323", N810_LM8323_ADDR);
403
qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
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/* LCD MIPI DBI-C controller (URAL) */
427
static void mipid_reset(struct mipid_s *s)
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(1 << 7) | /* Register loading OK. */
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(1 << 5) | /* The chip is attached. */
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(1 << 4); /* Display glass still in one piece. */
447
static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
449
struct mipid_s *s = (struct mipid_s *) opaque;
453
hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
455
if (s->p >= ARRAY_SIZE(s->resp))
458
ret = s->resp[s->p ++];
460
s->param[s->pm] = cmd;
468
case 0x01: /* SWRESET */
472
case 0x02: /* BSTROFF */
475
case 0x03: /* BSTRON */
479
case 0x04: /* RDDID */
481
s->resp[0] = (s->id >> 16) & 0xff;
482
s->resp[1] = (s->id >> 8) & 0xff;
483
s->resp[2] = (s->id >> 0) & 0xff;
486
case 0x06: /* RD_RED */
487
case 0x07: /* RD_GREEN */
488
/* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
489
* for the bootloader one needs to change this. */
490
case 0x08: /* RD_BLUE */
492
/* TODO: return first pixel components */
496
case 0x09: /* RDDST */
498
s->resp[0] = s->booster << 7;
499
s->resp[1] = (5 << 4) | (s->partial << 2) |
500
(s->sleep << 1) | s->normal;
501
s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
502
(s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
503
s->resp[3] = s->gamma << 6;
506
case 0x0a: /* RDDPM */
508
s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
509
(s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
511
case 0x0b: /* RDDMADCTR */
515
case 0x0c: /* RDDCOLMOD */
517
s->resp[0] = 5; /* 65K colours */
519
case 0x0d: /* RDDIM */
521
s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
523
case 0x0e: /* RDDSM */
525
s->resp[0] = s->te << 7;
527
case 0x0f: /* RDDSDR */
529
s->resp[0] = s->selfcheck;
532
case 0x10: /* SLPIN */
535
case 0x11: /* SLPOUT */
537
s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
540
case 0x12: /* PTLON */
545
case 0x13: /* NORON */
551
case 0x20: /* INVOFF */
554
case 0x21: /* INVON */
558
case 0x22: /* APOFF */
559
case 0x23: /* APON */
562
case 0x25: /* WRCNTR */
567
case 0x26: /* GAMSET */
569
s->gamma = ffs(s->param[0] & 0xf) - 1;
574
case 0x28: /* DISPOFF */
577
case 0x29: /* DISPON */
581
case 0x2a: /* CASET */
582
case 0x2b: /* RASET */
583
case 0x2c: /* RAMWR */
584
case 0x2d: /* RGBSET */
585
case 0x2e: /* RAMRD */
586
case 0x30: /* PTLAR */
587
case 0x33: /* SCRLAR */
590
case 0x34: /* TEOFF */
593
case 0x35: /* TEON */
600
case 0x36: /* MADCTR */
603
case 0x37: /* VSCSAD */
609
case 0x38: /* IDMOFF */
610
case 0x39: /* IDMON */
611
case 0x3a: /* COLMOD */
614
case 0xb0: /* CLKINT / DISCTL */
615
case 0xb1: /* CLKEXT */
620
case 0xb4: /* FRMSEL */
623
case 0xb5: /* FRM8SEL */
624
case 0xb6: /* TMPRNG / INIESC */
625
case 0xb7: /* TMPHIS / NOP2 */
626
case 0xb8: /* TMPREAD / MADCTL */
627
case 0xba: /* DISTCTR */
628
case 0xbb: /* EPVOL */
631
case 0xbd: /* Unknown */
637
case 0xc2: /* IFMOD */
642
case 0xc6: /* PWRCTL */
643
case 0xc7: /* PPWRCTL */
644
case 0xd0: /* EPWROUT */
645
case 0xd1: /* EPWRIN */
646
case 0xd4: /* RDEV */
647
case 0xd5: /* RDRR */
650
case 0xda: /* RDID1 */
652
s->resp[0] = (s->id >> 16) & 0xff;
654
case 0xdb: /* RDID2 */
656
s->resp[0] = (s->id >> 8) & 0xff;
658
case 0xdc: /* RDID3 */
660
s->resp[0] = (s->id >> 0) & 0xff;
665
qemu_log_mask(LOG_GUEST_ERROR,
666
"%s: unknown command %02x\n", __func__, s->cmd);
673
static void *mipid_init(void)
675
struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
683
static void n8x0_spi_setup(struct n800_s *s)
685
void *tsc = s->ts.opaque;
686
void *mipid = mipid_init();
688
omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
689
omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
692
/* This task is normally performed by the bootloader. If we're loading
693
* a kernel directly, we need to enable the Blizzard ourselves. */
694
static void n800_dss_init(struct rfbi_chip_s *chip)
698
chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
699
chip->write(chip->opaque, 1, 0x64);
700
chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
701
chip->write(chip->opaque, 1, 0x1e);
702
chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
703
chip->write(chip->opaque, 1, 0xe0);
704
chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
705
chip->write(chip->opaque, 1, 0x01);
706
chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
707
chip->write(chip->opaque, 1, 0x06);
708
chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
709
chip->write(chip->opaque, 1, 1); /* Enable bit */
711
chip->write(chip->opaque, 0, 0x6c);
712
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
713
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
714
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
715
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
716
chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
717
chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
718
chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
719
chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
720
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
721
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
722
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
723
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
724
chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
725
chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
726
chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
727
chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
728
chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
729
chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
731
fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
732
/* Display Memory Data Port */
733
chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
737
static void n8x0_dss_setup(struct n800_s *s)
739
s->blizzard.opaque = s1d13745_init(NULL);
740
s->blizzard.block = s1d13745_write_block;
741
s->blizzard.write = s1d13745_write;
742
s->blizzard.read = s1d13745_read;
744
omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
747
static void n8x0_cbus_setup(struct n800_s *s)
749
qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
750
qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
751
qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
753
CBus *cbus = cbus_init(dat_out);
755
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
756
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
757
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
759
cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
760
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
763
static void n8x0_uart_setup(struct n800_s *s)
765
CharDriverState *radio = uart_hci_init(
766
qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
768
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
769
csrhci_pins_get(radio)[csrhci_pin_reset]);
770
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
771
csrhci_pins_get(radio)[csrhci_pin_wakeup]);
773
omap_uart_attach(s->mpu->uart[BT_UART], radio);
776
static void n8x0_usb_setup(struct n800_s *s)
779
s->usb = qdev_create(NULL, "tusb6010");
780
dev = SYS_BUS_DEVICE(s->usb);
781
qdev_init_nofail(s->usb);
782
sysbus_connect_irq(dev, 0,
783
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
784
/* Using the NOR interface */
785
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
786
sysbus_mmio_get_region(dev, 0));
787
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
788
sysbus_mmio_get_region(dev, 1));
789
qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
790
qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
793
/* Setup done before the main bootloader starts by some early setup code
794
* - used when we want to run the main bootloader in emulation. This
795
* isn't documented. */
796
static uint32_t n800_pinout[104] = {
797
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
798
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
799
0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
800
0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
801
0x01241800, 0x18181818, 0x000000f0, 0x01300000,
802
0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
803
0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
804
0x007c0000, 0x00000000, 0x00000088, 0x00840000,
805
0x00000000, 0x00000094, 0x00980300, 0x0f180003,
806
0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
807
0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
808
0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
809
0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
810
0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
811
0x00000000, 0x00000038, 0x00340000, 0x00000000,
812
0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
813
0x005c0808, 0x08080808, 0x08080058, 0x00540808,
814
0x08080808, 0x0808006c, 0x00680808, 0x08080808,
815
0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
816
0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
817
0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
818
0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
819
0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
820
0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
821
0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
822
0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
825
static void n800_setup_nolo_tags(void *sram_base)
828
uint32_t *p = sram_base + 0x8000;
829
uint32_t *v = sram_base + 0xa000;
831
memset(p, 0, 0x3000);
833
strcpy((void *) (p + 0), "QEMU N800");
835
strcpy((void *) (p + 8), "F5");
837
stl_raw(p + 10, 0x04f70000);
838
strcpy((void *) (p + 9), "RX-34");
840
/* RAM size in MB? */
841
stl_raw(p + 12, 0x80);
843
/* Pointer to the list of tags */
844
stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
846
/* The NOLO tags start here */
847
p = sram_base + 0x9000;
848
#define ADD_TAG(tag, len) \
849
stw_raw((uint16_t *) p + 0, tag); \
850
stw_raw((uint16_t *) p + 1, len); p ++; \
851
stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
853
/* OMAP STI console? Pin out settings? */
854
ADD_TAG(0x6e01, 414);
855
for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
856
stl_raw(v ++, n800_pinout[i]);
858
/* Kernel memsize? */
862
/* NOLO serial console */
864
stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
867
/* CBUS settings (Retu/AVilma) */
869
stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
870
stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
871
stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
875
/* Nokia ASIC BB5 (Retu/Tahvo) */
877
stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
878
stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
883
stw_raw((uint16_t *) v + 0, 30); /* ??? */
884
stw_raw((uint16_t *) v + 1, 24); /* ??? */
890
stw_raw((uint16_t *) (v ++), 15); /* ??? */
893
/* I^2C (Menelaus) */
895
stl_raw(v ++, 0x00720000); /* ??? */
899
stw_raw((uint16_t *) v + 0, 94); /* ??? */
900
stw_raw((uint16_t *) v + 1, 23); /* ??? */
901
stw_raw((uint16_t *) v + 2, 0); /* ??? */
904
/* OMAP gpio switch info */
906
strcpy((void *) v, "bat_cover"); v += 3;
907
stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
908
stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
910
strcpy((void *) v, "cam_act"); v += 3;
911
stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
912
stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
914
strcpy((void *) v, "cam_turn"); v += 3;
915
stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
916
stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
918
strcpy((void *) v, "headphone"); v += 3;
919
stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
920
stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
925
stl_raw(v ++, 0x5c623d01); /* ??? */
926
stl_raw(v ++, 0x00000201); /* ??? */
927
stl_raw(v ++, 0x00000000); /* ??? */
929
/* CX3110x WLAN settings */
931
stl_raw(v ++, 0x00610025); /* ??? */
932
stl_raw(v ++, 0xffff0057); /* ??? */
934
/* MMC host settings */
936
stl_raw(v ++, 0xffff000f); /* ??? */
937
stl_raw(v ++, 0xffffffff); /* ??? */
938
stl_raw(v ++, 0x00000060); /* ??? */
940
/* OneNAND chip select */
942
stl_raw(v ++, 0x00000401); /* ??? */
943
stl_raw(v ++, 0x0002003a); /* ??? */
944
stl_raw(v ++, 0x00000002); /* ??? */
946
/* TEA5761 sensor settings */
948
stl_raw(v ++, 93); /* GPIO num ??? */
954
/* Kernel UART / console */
958
/* End of the list */
959
stl_raw(p ++, 0x00000000);
960
stl_raw(p ++, 0x00000000);
963
/* This task is normally performed by the bootloader. If we're loading
964
* a kernel directly, we need to set up GPMC mappings ourselves. */
965
static void n800_gpmc_init(struct n800_s *s)
968
(0xf << 8) | /* MASKADDRESS */
969
(1 << 6) | /* CSVALID */
970
(4 << 0); /* BASEADDRESS */
972
cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
973
&config7, sizeof(config7));
976
/* Setup sequence done by the bootloader */
977
static void n8x0_boot_init(void *opaque)
979
struct n800_s *s = (struct n800_s *) opaque;
983
#define omap_writel(addr, val) \
985
cpu_physical_memory_write(addr, &buf, sizeof(buf))
987
omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
988
omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
989
omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
990
omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
991
omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
992
omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
993
omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
994
omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
995
omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
996
omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
997
omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
998
omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
999
omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1000
omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1001
omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1002
omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1003
omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1004
omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1005
omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1006
omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1007
omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1008
omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1009
omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1010
omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1011
omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1012
omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1013
omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1014
omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1015
omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1016
omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1017
omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1018
omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1019
omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1020
omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1021
omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1022
(0x78 << 12) | (6 << 8));
1023
omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1029
n800_dss_init(&s->blizzard);
1032
s->mpu->cpu->env.GE = 0x5;
1034
/* If the machine has a slided keyboard, open it */
1036
qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1039
#define OMAP_TAG_NOKIA_BT 0x4e01
1040
#define OMAP_TAG_WLAN_CX3110X 0x4e02
1041
#define OMAP_TAG_CBUS 0x4e03
1042
#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1044
static struct omap_gpiosw_info_s {
1048
} n800_gpiosw_info[] = {
1050
"bat_cover", N800_BAT_COVER_GPIO,
1051
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1053
"cam_act", N800_CAM_ACT_GPIO,
1054
OMAP_GPIOSW_TYPE_ACTIVITY,
1056
"cam_turn", N800_CAM_TURN_GPIO,
1057
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1059
"headphone", N8X0_HEADPHONE_GPIO,
1060
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1063
}, n810_gpiosw_info[] = {
1065
"gps_reset", N810_GPS_RESET_GPIO,
1066
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1068
"gps_wakeup", N810_GPS_WAKEUP_GPIO,
1069
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1071
"headphone", N8X0_HEADPHONE_GPIO,
1072
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1074
"kb_lock", N810_KB_LOCK_GPIO,
1075
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1077
"sleepx_led", N810_SLEEPX_LED_GPIO,
1078
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1080
"slide", N810_SLIDE_GPIO,
1081
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1086
static struct omap_partition_info_s {
1091
} n800_part_info[] = {
1092
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
1093
{ 0x00020000, 0x00060000, 0x0, "config" },
1094
{ 0x00080000, 0x00200000, 0x0, "kernel" },
1095
{ 0x00280000, 0x00200000, 0x3, "initfs" },
1096
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1099
}, n810_part_info[] = {
1100
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
1101
{ 0x00020000, 0x00060000, 0x0, "config" },
1102
{ 0x00080000, 0x00220000, 0x0, "kernel" },
1103
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
1104
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1109
static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1111
static int n8x0_atag_setup(void *p, int model)
1116
struct omap_gpiosw_info_s *gpiosw;
1117
struct omap_partition_info_s *partition;
1122
stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1123
stw_raw(w ++, 4); /* u16 len */
1124
stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1128
stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1129
stw_raw(w ++, 4); /* u16 len */
1130
stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1131
stw_raw(w ++, 115200); /* u32 console_speed */
1134
stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1135
stw_raw(w ++, 36); /* u16 len */
1136
strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1138
strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1140
stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1141
stw_raw(w ++, 24); /* u8 data_lines */
1143
stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1144
stw_raw(w ++, 8); /* u16 len */
1145
stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1146
stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1147
stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1150
stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1151
stw_raw(w ++, 4); /* u16 len */
1152
stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1153
stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1155
gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1156
for (; gpiosw->name; gpiosw ++) {
1157
stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1158
stw_raw(w ++, 20); /* u16 len */
1159
strcpy((void *) w, gpiosw->name); /* char name[12] */
1161
stw_raw(w ++, gpiosw->line); /* u16 gpio */
1162
stw_raw(w ++, gpiosw->type);
1167
stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1168
stw_raw(w ++, 12); /* u16 len */
1170
stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1171
stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1172
stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1173
stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1174
stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1175
memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1177
stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1180
stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1181
stw_raw(w ++, 8); /* u16 len */
1182
stw_raw(w ++, 0x25); /* u8 chip_type */
1183
stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1184
stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1185
stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1187
stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1188
stw_raw(w ++, 16); /* u16 len */
1190
stw_raw(w ++, 0x23f); /* unsigned flags */
1191
stw_raw(w ++, -1); /* s16 power_pin */
1192
stw_raw(w ++, -1); /* s16 switch_pin */
1193
stw_raw(w ++, -1); /* s16 wp_pin */
1194
stw_raw(w ++, 0x240); /* unsigned flags */
1195
stw_raw(w ++, 0xc000); /* s16 power_pin */
1196
stw_raw(w ++, 0x0248); /* s16 switch_pin */
1197
stw_raw(w ++, 0xc000); /* s16 wp_pin */
1199
stw_raw(w ++, 0xf); /* unsigned flags */
1200
stw_raw(w ++, -1); /* s16 power_pin */
1201
stw_raw(w ++, -1); /* s16 switch_pin */
1202
stw_raw(w ++, -1); /* s16 wp_pin */
1203
stw_raw(w ++, 0); /* unsigned flags */
1204
stw_raw(w ++, 0); /* s16 power_pin */
1205
stw_raw(w ++, 0); /* s16 switch_pin */
1206
stw_raw(w ++, 0); /* s16 wp_pin */
1209
stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1210
stw_raw(w ++, 4); /* u16 len */
1211
stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1214
partition = (model == 810) ? n810_part_info : n800_part_info;
1215
for (; partition->name; partition ++) {
1216
stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1217
stw_raw(w ++, 28); /* u16 len */
1218
strcpy((void *) w, partition->name); /* char name[16] */
1219
l = (void *) (w + 8);
1220
stl_raw(l ++, partition->size); /* unsigned int size */
1221
stl_raw(l ++, partition->offset); /* unsigned int offset */
1222
stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1226
stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1227
stw_raw(w ++, 12); /* u16 len */
1229
strcpy((void *) w, "por"); /* char reason_str[12] */
1230
strcpy((void *) w, "charger"); /* char reason_str[12] */
1231
strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1232
strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1233
strcpy((void *) w, "mbus"); /* char reason_str[12] */
1234
strcpy((void *) w, "unknown"); /* char reason_str[12] */
1235
strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1236
strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1237
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1238
strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1240
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1244
tag = (model == 810) ? "RX-44" : "RX-34";
1245
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1246
stw_raw(w ++, 24); /* u16 len */
1247
strcpy((void *) w, "product"); /* char component[12] */
1249
strcpy((void *) w, tag); /* char version[12] */
1252
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1253
stw_raw(w ++, 24); /* u16 len */
1254
strcpy((void *) w, "hw-build"); /* char component[12] */
1256
strcpy((void *) w, "QEMU ");
1257
pstrcat((void *) w, 12, qemu_get_version()); /* char version[12] */
1260
tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1261
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1262
stw_raw(w ++, 24); /* u16 len */
1263
strcpy((void *) w, "nolo"); /* char component[12] */
1265
strcpy((void *) w, tag); /* char version[12] */
1268
return (void *) w - p;
1271
static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1273
return n8x0_atag_setup(p, 800);
1276
static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1278
return n8x0_atag_setup(p, 810);
1281
static void n8x0_init(QEMUMachineInitArgs *args,
1282
struct arm_boot_info *binfo, int model)
1284
MemoryRegion *sysmem = get_system_memory();
1285
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1286
int sdram_size = binfo->ram_size;
1288
s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model);
1290
/* Setup peripherals
1292
* Believed external peripherals layout in the N810:
1297
* Conexant cx3110x (WLAN)
1298
* optional: pc2400m (WiMAX)
1300
* TLV320AIC33 (audio codec)
1301
* TCM825x (camera by Toshiba)
1302
* lp5521 (clever LEDs)
1303
* tsl2563 (light sensor, hwmon, model 7, rev. 0)
1304
* lm8323 (keypad, manf 00, rev 04)
1306
* tmp105 (temperature sensor, hwmon)
1308
* (somewhere on i2c - maybe N800-only)
1309
* tea5761 (FM tuner)
1312
* (some serial port)
1313
* csr41814 (Bluetooth)
1319
n800_tsc_kbd_setup(s);
1320
else if (model == 810) {
1328
if (usb_enabled(false)) {
1332
if (args->kernel_filename) {
1333
/* Or at the linux loader. */
1334
binfo->kernel_filename = args->kernel_filename;
1335
binfo->kernel_cmdline = args->kernel_cmdline;
1336
binfo->initrd_filename = args->initrd_filename;
1337
arm_load_kernel(s->mpu->cpu, binfo);
1339
qemu_register_reset(n8x0_boot_init, s);
1342
if (option_rom[0].name &&
1343
(args->boot_device[0] == 'n' || !args->kernel_filename)) {
1344
uint8_t nolo_tags[0x10000];
1345
/* No, wait, better start at the ROM. */
1346
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1348
/* This is intended for loading the `secondary.bin' program from
1349
* Nokia images (the NOLO bootloader). The entry point seems
1350
* to be at OMAP2_Q2_BASE + 0x400000.
1352
* The `2nd.bin' files contain some kind of earlier boot code and
1353
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
1355
* The code above is for loading the `zImage' file from Nokia
1357
load_image_targphys(option_rom[0].name,
1358
OMAP2_Q2_BASE + 0x400000,
1359
sdram_size - 0x400000);
1361
n800_setup_nolo_tags(nolo_tags);
1362
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1366
static struct arm_boot_info n800_binfo = {
1367
.loader_start = OMAP2_Q2_BASE,
1368
/* Actually two chips of 0x4000000 bytes each */
1369
.ram_size = 0x08000000,
1371
.atag_board = n800_atag_setup,
1374
static struct arm_boot_info n810_binfo = {
1375
.loader_start = OMAP2_Q2_BASE,
1376
/* Actually two chips of 0x4000000 bytes each */
1377
.ram_size = 0x08000000,
1378
/* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1379
* used by some older versions of the bootloader and 5555 is used
1380
* instead (including versions that shipped with many devices). */
1382
.atag_board = n810_atag_setup,
1385
static void n800_init(QEMUMachineInitArgs *args)
1387
return n8x0_init(args, &n800_binfo, 800);
1390
static void n810_init(QEMUMachineInitArgs *args)
1392
return n8x0_init(args, &n810_binfo, 810);
1395
static QEMUMachine n800_machine = {
1397
.desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1399
DEFAULT_MACHINE_OPTIONS,
1402
static QEMUMachine n810_machine = {
1404
.desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1406
DEFAULT_MACHINE_OPTIONS,
1409
static void nseries_machine_init(void)
1411
qemu_register_machine(&n800_machine);
1412
qemu_register_machine(&n810_machine);
1415
machine_init(nseries_machine_init);