456
456
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
457
dma_memory_read(ehci->dma, addr, buf, sizeof(*buf));
457
dma_memory_read(ehci->as, addr, buf, sizeof(*buf));
458
458
*buf = le32_to_cpu(*buf);
477
477
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
478
478
uint32_t tmp = cpu_to_le32(*buf);
479
dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp));
479
dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp));
1070
1070
*portsc &= ~PORTSC_RO_MASK;
1071
1071
*portsc |= val;
1072
trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
1072
trace_usb_ehci_portsc_change(addr + s->portscbase, addr >> 2, *portsc, old);
1075
1075
static void ehci_opreg_write(void *ptr, hwaddr addr,
1245
1245
cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1246
1246
bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1247
1247
offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1248
qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma);
1248
qemu_sglist_init(&p->sgl, p->queue->ehci->device, 5, p->queue->ehci->as);
1250
1250
while (bytes > 0) {
1251
1251
if (cpage > 4) {
2511
void usb_ehci_initfn(EHCIState *s, DeviceState *dev)
2511
void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)
2515
if (s->portnr > NB_PORTS) {
2516
error_setg(errp, "Too many ports! Max. port number is %d.",
2521
usb_bus_new(&s->bus, &ehci_bus_ops, dev);
2522
for (i = 0; i < s->portnr; i++) {
2523
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2524
USB_SPEED_MASK_HIGH);
2525
s->ports[i].dev = 0;
2528
s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2529
s->async_bh = qemu_bh_new(ehci_frame_timer, s);
2532
qemu_register_reset(ehci_reset, s);
2533
qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s);
2536
void usb_ehci_init(EHCIState *s, DeviceState *dev)
2515
2538
/* 2.2 host controller interface version */
2516
2539
s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
2517
2540
s->caps[0x01] = 0x00;
2518
2541
s->caps[0x02] = 0x00;
2519
2542
s->caps[0x03] = 0x01; /* HC version */
2520
s->caps[0x04] = NB_PORTS; /* Number of downstream ports */
2543
s->caps[0x04] = s->portnr; /* Number of downstream ports */
2521
2544
s->caps[0x05] = 0x00; /* No companion ports at present */
2522
2545
s->caps[0x06] = 0x00;
2523
2546
s->caps[0x07] = 0x00;
2525
2548
s->caps[0x0a] = 0x00;
2526
2549
s->caps[0x0b] = 0x00;
2528
usb_bus_new(&s->bus, &ehci_bus_ops, dev);
2529
for(i = 0; i < NB_PORTS; i++) {
2530
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2531
USB_SPEED_MASK_HIGH);
2532
s->ports[i].dev = 0;
2535
s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2536
s->async_bh = qemu_bh_new(ehci_frame_timer, s);
2537
2551
QTAILQ_INIT(&s->aqueues);
2538
2552
QTAILQ_INIT(&s->pqueues);
2539
2553
usb_packet_init(&s->ipacket);
2541
qemu_register_reset(ehci_reset, s);
2542
qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s);
2544
memory_region_init(&s->mem, "ehci", MMIO_SIZE);
2545
memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s,
2555
memory_region_init(&s->mem, OBJECT(dev), "ehci", MMIO_SIZE);
2556
memory_region_init_io(&s->mem_caps, OBJECT(dev), &ehci_mmio_caps_ops, s,
2546
2557
"capabilities", CAPA_SIZE);
2547
memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s,
2548
"operational", PORTSC_BEGIN);
2549
memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s,
2550
"ports", PORTSC_END - PORTSC_BEGIN);
2558
memory_region_init_io(&s->mem_opreg, OBJECT(dev), &ehci_mmio_opreg_ops, s,
2559
"operational", s->portscbase);
2560
memory_region_init_io(&s->mem_ports, OBJECT(dev), &ehci_mmio_port_ops, s,
2561
"ports", 4 * s->portnr);
2552
2563
memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps);
2553
2564
memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
2554
memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN,
2565
memory_region_add_subregion(&s->mem, s->opregbase + s->portscbase,
2555
2566
&s->mem_ports);