6514
6469
PPC_MEM_TLBIA | PPC_74xx_TLB |
6515
6470
PPC_SEGMENT | PPC_EXTERN |
6472
pcc->msr_mask = 0x000000000205FF77ULL;
6473
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6474
pcc->excp_model = POWERPC_EXCP_74xx;
6475
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6476
pcc->bfd_mach = bfd_mach_ppc_7400;
6477
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6478
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6479
POWERPC_FLAG_BUS_CLK;
6482
static void init_proc_e600 (CPUPPCState *env)
6484
gen_spr_ne_601(env);
6488
/* 74xx specific SPR */
6490
/* XXX : not implemented */
6491
spr_register(env, SPR_UBAMR, "UBAMR",
6492
&spr_read_ureg, SPR_NOACCESS,
6493
&spr_read_ureg, SPR_NOACCESS,
6495
/* XXX : not implemented */
6496
spr_register(env, SPR_LDSTCR, "LDSTCR",
6497
SPR_NOACCESS, SPR_NOACCESS,
6498
&spr_read_generic, &spr_write_generic,
6500
/* XXX : not implemented */
6501
spr_register(env, SPR_ICTRL, "ICTRL",
6502
SPR_NOACCESS, SPR_NOACCESS,
6503
&spr_read_generic, &spr_write_generic,
6505
/* XXX : not implemented */
6506
spr_register(env, SPR_MSSSR0, "MSSSR0",
6507
SPR_NOACCESS, SPR_NOACCESS,
6508
&spr_read_generic, &spr_write_generic,
6510
/* XXX : not implemented */
6511
spr_register(env, SPR_PMC5, "PMC5",
6512
SPR_NOACCESS, SPR_NOACCESS,
6513
&spr_read_generic, &spr_write_generic,
6515
/* XXX : not implemented */
6516
spr_register(env, SPR_UPMC5, "UPMC5",
6517
&spr_read_ureg, SPR_NOACCESS,
6518
&spr_read_ureg, SPR_NOACCESS,
6520
/* XXX : not implemented */
6521
spr_register(env, SPR_PMC6, "PMC6",
6522
SPR_NOACCESS, SPR_NOACCESS,
6523
&spr_read_generic, &spr_write_generic,
6525
/* XXX : not implemented */
6526
spr_register(env, SPR_UPMC6, "UPMC6",
6527
&spr_read_ureg, SPR_NOACCESS,
6528
&spr_read_ureg, SPR_NOACCESS,
6531
spr_register(env, SPR_SPRG4, "SPRG4",
6532
SPR_NOACCESS, SPR_NOACCESS,
6533
&spr_read_generic, &spr_write_generic,
6535
spr_register(env, SPR_USPRG4, "USPRG4",
6536
&spr_read_ureg, SPR_NOACCESS,
6537
&spr_read_ureg, SPR_NOACCESS,
6539
spr_register(env, SPR_SPRG5, "SPRG5",
6540
SPR_NOACCESS, SPR_NOACCESS,
6541
&spr_read_generic, &spr_write_generic,
6543
spr_register(env, SPR_USPRG5, "USPRG5",
6544
&spr_read_ureg, SPR_NOACCESS,
6545
&spr_read_ureg, SPR_NOACCESS,
6547
spr_register(env, SPR_SPRG6, "SPRG6",
6548
SPR_NOACCESS, SPR_NOACCESS,
6549
&spr_read_generic, &spr_write_generic,
6551
spr_register(env, SPR_USPRG6, "USPRG6",
6552
&spr_read_ureg, SPR_NOACCESS,
6553
&spr_read_ureg, SPR_NOACCESS,
6555
spr_register(env, SPR_SPRG7, "SPRG7",
6556
SPR_NOACCESS, SPR_NOACCESS,
6557
&spr_read_generic, &spr_write_generic,
6559
spr_register(env, SPR_USPRG7, "USPRG7",
6560
&spr_read_ureg, SPR_NOACCESS,
6561
&spr_read_ureg, SPR_NOACCESS,
6563
/* Memory management */
6566
gen_74xx_soft_tlb(env, 128, 2);
6567
init_excp_7450(env);
6568
env->dcache_line_size = 32;
6569
env->icache_line_size = 32;
6570
/* Allocate hardware IRQ controller */
6571
ppc6xx_irq_init(env);
6574
POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6576
DeviceClass *dc = DEVICE_CLASS(oc);
6577
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6579
dc->desc = "PowerPC e600";
6580
pcc->init_proc = init_proc_e600;
6581
pcc->check_pow = check_pow_hid0_74xx;
6582
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6583
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6584
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6586
PPC_CACHE | PPC_CACHE_ICBI |
6587
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6588
PPC_MEM_SYNC | PPC_MEM_EIEIO |
6589
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6590
PPC_MEM_TLBIA | PPC_74xx_TLB |
6591
PPC_SEGMENT | PPC_EXTERN |
6517
6593
pcc->insns_flags2 = PPC_NONE;
6518
6594
pcc->msr_mask = 0x000000000205FF77ULL;
6519
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6595
pcc->mmu_model = POWERPC_MMU_32B;
6596
#if defined(CONFIG_SOFTMMU)
6597
pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6520
6599
pcc->excp_model = POWERPC_EXCP_74xx;
6521
6600
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6522
6601
pcc->bfd_mach = bfd_mach_ppc_7400;
6948
7023
POWERPC_FLAG_BUS_CLK;
7026
static void init_proc_power5plus(CPUPPCState *env)
7028
gen_spr_ne_601(env);
7032
/* Hardware implementation registers */
7033
/* XXX : not implemented */
7034
spr_register(env, SPR_HID0, "HID0",
7035
SPR_NOACCESS, SPR_NOACCESS,
7036
&spr_read_generic, &spr_write_clear,
7038
/* XXX : not implemented */
7039
spr_register(env, SPR_HID1, "HID1",
7040
SPR_NOACCESS, SPR_NOACCESS,
7041
&spr_read_generic, &spr_write_generic,
7043
/* XXX : not implemented */
7044
spr_register(env, SPR_750FX_HID2, "HID2",
7045
SPR_NOACCESS, SPR_NOACCESS,
7046
&spr_read_generic, &spr_write_generic,
7048
/* XXX : not implemented */
7049
spr_register(env, SPR_970_HID5, "HID5",
7050
SPR_NOACCESS, SPR_NOACCESS,
7051
&spr_read_generic, &spr_write_generic,
7052
POWERPC970_HID5_INIT);
7053
/* XXX : not implemented */
7054
spr_register(env, SPR_L2CR, "L2CR",
7055
SPR_NOACCESS, SPR_NOACCESS,
7056
&spr_read_generic, NULL,
7058
/* Memory management */
7059
/* XXX: not correct */
7061
/* XXX : not implemented */
7062
spr_register(env, SPR_MMUCFG, "MMUCFG",
7063
SPR_NOACCESS, SPR_NOACCESS,
7064
&spr_read_generic, SPR_NOACCESS,
7065
0x00000000); /* TOFIX */
7066
/* XXX : not implemented */
7067
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
7068
SPR_NOACCESS, SPR_NOACCESS,
7069
&spr_read_generic, &spr_write_generic,
7070
0x00000000); /* TOFIX */
7071
spr_register(env, SPR_HIOR, "SPR_HIOR",
7072
SPR_NOACCESS, SPR_NOACCESS,
7073
&spr_read_hior, &spr_write_hior,
7075
spr_register(env, SPR_CTRL, "SPR_CTRL",
7076
SPR_NOACCESS, SPR_NOACCESS,
7077
&spr_read_generic, &spr_write_generic,
7079
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7080
SPR_NOACCESS, SPR_NOACCESS,
7081
&spr_read_generic, &spr_write_generic,
7083
spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7084
&spr_read_generic, &spr_write_generic,
7085
&spr_read_generic, &spr_write_generic,
7087
#if !defined(CONFIG_USER_ONLY)
7091
env->dcache_line_size = 128;
7092
env->icache_line_size = 128;
7093
/* Allocate hardware IRQ controller */
7094
ppc970_irq_init(env);
7095
/* Can't find information on what this should be on reset. This
7096
* value is the one used by 74xx processors. */
7097
vscr_init(env, 0x00010000);
7100
POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7102
DeviceClass *dc = DEVICE_CLASS(oc);
7103
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7105
dc->desc = "POWER5+";
7106
pcc->init_proc = init_proc_power5plus;
7107
pcc->check_pow = check_pow_970FX;
7108
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7109
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7110
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7112
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7113
PPC_MEM_SYNC | PPC_MEM_EIEIO |
7114
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7116
PPC_SEGMENT_64B | PPC_SLBI;
7117
pcc->msr_mask = 0x800000000204FF36ULL;
7118
pcc->mmu_model = POWERPC_MMU_64B;
7119
#if defined(CONFIG_SOFTMMU)
7120
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7122
pcc->excp_model = POWERPC_EXCP_970;
7123
pcc->bus_model = PPC_FLAGS_INPUT_970;
7124
pcc->bfd_mach = bfd_mach_ppc64;
7125
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7126
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7127
POWERPC_FLAG_BUS_CLK;
6951
7130
static void init_proc_POWER7 (CPUPPCState *env)
6953
7132
gen_spr_ne_601(env);
7061
7240
pcc->l1_dcache_size = 0x8000;
7062
7241
pcc->l1_icache_size = 0x8000;
7244
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7246
DeviceClass *dc = DEVICE_CLASS(oc);
7247
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7249
dc->desc = "POWER8";
7250
pcc->init_proc = init_proc_POWER7;
7251
pcc->check_pow = check_pow_nocheck;
7252
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7253
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7254
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7256
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7257
PPC_MEM_SYNC | PPC_MEM_EIEIO |
7258
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7259
PPC_64B | PPC_ALTIVEC |
7260
PPC_SEGMENT_64B | PPC_SLBI |
7261
PPC_POPCNTB | PPC_POPCNTWD;
7262
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
7263
pcc->msr_mask = 0x800000000204FF36ULL;
7264
pcc->mmu_model = POWERPC_MMU_2_06;
7265
#if defined(CONFIG_SOFTMMU)
7266
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7268
pcc->excp_model = POWERPC_EXCP_POWER7;
7269
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7270
pcc->bfd_mach = bfd_mach_ppc64;
7271
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7272
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7273
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7274
pcc->l1_dcache_size = 0x8000;
7275
pcc->l1_icache_size = 0x8000;
7064
7277
#endif /* defined (TARGET_PPC64) */
7740
7953
init_ppc_proc(cpu);
7742
7955
if (pcc->insns_flags & PPC_FLOAT) {
7743
gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
7956
gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
7744
7957
33, "power-fpu.xml", 0);
7746
7959
if (pcc->insns_flags & PPC_ALTIVEC) {
7747
gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
7960
gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
7748
7961
34, "power-altivec.xml", 0);
7750
7963
if (pcc->insns_flags & PPC_SPE) {
7751
gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
7964
gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
7752
7965
34, "power-spe.xml", 0);
7755
qemu_init_vcpu(env);
7757
7970
pcc->parent_realize(dev, errp);
7759
7972
#if defined(PPC_DUMP_CPU)
7974
CPUPPCState *env = &cpu->env;
7761
7975
const char *mmu_model, *excp_model, *bus_model;
7762
7976
switch (env->mmu_model) {
7763
7977
case POWERPC_MMU_32B: