2
* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
4
* Copyright (c) 2006 Openedhand Ltd.
5
* Written by Andrzej Zaborowski <balrog@zabor.org>
7
* This code is licensed under the GPLv2.
9
* Contributions after 2012-01-13 are licensed under the terms of the
10
* GNU GPL, version 2 or (at your option) any later version.
14
#include "hw/arm/pxa.h"
18
struct PXA2xxMMCIState {
47
uint16_t resp_fifo[9];
54
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
55
#define MMC_STAT 0x04 /* MMC Status register */
56
#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
57
#define MMC_SPI 0x0c /* MMC SPI Mode register */
58
#define MMC_CMDAT 0x10 /* MMC Command/Data register */
59
#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
60
#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
61
#define MMC_BLKLEN 0x1c /* MMC Block Length register */
62
#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
63
#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
64
#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
65
#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
66
#define MMC_CMD 0x30 /* MMC Command register */
67
#define MMC_ARGH 0x34 /* MMC Argument High register */
68
#define MMC_ARGL 0x38 /* MMC Argument Low register */
69
#define MMC_RES 0x3c /* MMC Response FIFO */
70
#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
71
#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
72
#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
73
#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
76
#define STRPCL_STOP_CLK (1 << 0)
77
#define STRPCL_STRT_CLK (1 << 1)
78
#define STAT_TOUT_RES (1 << 1)
79
#define STAT_CLK_EN (1 << 8)
80
#define STAT_DATA_DONE (1 << 11)
81
#define STAT_PRG_DONE (1 << 12)
82
#define STAT_END_CMDRES (1 << 13)
83
#define SPI_SPI_MODE (1 << 0)
84
#define CMDAT_RES_TYPE (3 << 0)
85
#define CMDAT_DATA_EN (1 << 2)
86
#define CMDAT_WR_RD (1 << 3)
87
#define CMDAT_DMA_EN (1 << 7)
88
#define CMDAT_STOP_TRAN (1 << 10)
89
#define INT_DATA_DONE (1 << 0)
90
#define INT_PRG_DONE (1 << 1)
91
#define INT_END_CMD (1 << 2)
92
#define INT_STOP_CMD (1 << 3)
93
#define INT_CLK_OFF (1 << 4)
94
#define INT_RXFIFO_REQ (1 << 5)
95
#define INT_TXFIFO_REQ (1 << 6)
96
#define INT_TINT (1 << 7)
97
#define INT_DAT_ERR (1 << 8)
98
#define INT_RES_ERR (1 << 9)
99
#define INT_RD_STALLED (1 << 10)
100
#define INT_SDIO_INT (1 << 11)
101
#define INT_SDIO_SACK (1 << 12)
102
#define PRTBUF_PRT_BUF (1 << 0)
104
/* Route internal interrupt lines to the global IC and DMA */
105
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
107
uint32_t mask = s->intmask;
108
if (s->cmdat & CMDAT_DMA_EN) {
109
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
111
qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
112
qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
115
qemu_set_irq(s->irq, !!(s->intreq & ~mask));
118
static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
123
if (s->cmdat & CMDAT_WR_RD) {
124
while (s->bytesleft && s->tx_len) {
125
sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
131
s->intreq |= INT_TXFIFO_REQ;
133
while (s->bytesleft && s->rx_len < 32) {
134
s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
135
sd_read_data(s->card);
137
s->intreq |= INT_RXFIFO_REQ;
142
s->intreq |= INT_DATA_DONE;
143
s->status |= STAT_DATA_DONE;
145
if (s->cmdat & CMDAT_WR_RD) {
146
s->intreq |= INT_PRG_DONE;
147
s->status |= STAT_PRG_DONE;
151
pxa2xx_mmci_int_update(s);
154
static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
158
uint8_t response[16];
165
request.cmd = s->cmd;
166
request.arg = s->arg;
167
request.crc = 0; /* FIXME */
169
rsplen = sd_do_command(s->card, &request, response);
170
s->intreq |= INT_END_CMD;
172
memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
173
switch (s->cmdat & CMDAT_RES_TYPE) {
174
#define PXAMMCI_RESP(wd, value0, value1) \
175
s->resp_fifo[(wd) + 0] |= (value0); \
176
s->resp_fifo[(wd) + 1] |= (value1) << 8;
177
case 0: /* No response */
180
case 1: /* R1, R4, R5 or R6 */
196
for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
197
PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
199
s->status |= STAT_END_CMDRES;
201
if (!(s->cmdat & CMDAT_DATA_EN))
204
s->bytesleft = s->numblk * s->blklen;
211
s->status |= STAT_TOUT_RES;
215
pxa2xx_mmci_fifo_update(s);
218
static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
220
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
249
return s->cmd | 0x40;
253
return s->arg & 0xffff;
256
return s->resp_fifo[s->resp_len ++];
260
while (s->ac_width -- && s->rx_len) {
261
ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
265
s->intreq &= ~INT_RXFIFO_REQ;
266
pxa2xx_mmci_fifo_update(s);
273
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
279
static void pxa2xx_mmci_write(void *opaque,
280
hwaddr offset, uint32_t value)
282
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
286
if (value & STRPCL_STRT_CLK) {
287
s->status |= STAT_CLK_EN;
288
s->intreq &= ~INT_CLK_OFF;
290
if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
291
s->status &= STAT_CLK_EN;
292
pxa2xx_mmci_wakequeues(s);
296
if (value & STRPCL_STOP_CLK) {
297
s->status &= ~STAT_CLK_EN;
298
s->intreq |= INT_CLK_OFF;
302
pxa2xx_mmci_int_update(s);
306
s->clkrt = value & 7;
310
s->spi = value & 0xf;
311
if (value & SPI_SPI_MODE)
312
printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
316
s->cmdat = value & 0x3dff;
319
if (!(value & CMDAT_STOP_TRAN)) {
320
s->status &= STAT_CLK_EN;
322
if (s->status & STAT_CLK_EN)
323
pxa2xx_mmci_wakequeues(s);
326
pxa2xx_mmci_int_update(s);
330
s->resp_tout = value & 0x7f;
334
s->read_tout = value & 0xffff;
338
s->blklen = value & 0xfff;
342
s->numblk = value & 0xffff;
346
if (value & PRTBUF_PRT_BUF) {
350
pxa2xx_mmci_fifo_update(s);
354
s->intmask = value & 0x1fff;
355
pxa2xx_mmci_int_update(s);
359
s->cmd = value & 0x3f;
363
s->arg &= 0x0000ffff;
364
s->arg |= value << 16;
368
s->arg &= 0xffff0000;
369
s->arg |= value & 0x0000ffff;
373
while (s->ac_width -- && s->tx_len < 0x20)
374
s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
375
(value >> (s->ac_width << 3)) & 0xff;
376
s->intreq &= ~INT_TXFIFO_REQ;
377
pxa2xx_mmci_fifo_update(s);
385
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
389
static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset)
391
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
393
return pxa2xx_mmci_read(opaque, offset);
396
static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset)
398
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
400
return pxa2xx_mmci_read(opaque, offset);
403
static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset)
405
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
407
return pxa2xx_mmci_read(opaque, offset);
410
static void pxa2xx_mmci_writeb(void *opaque,
411
hwaddr offset, uint32_t value)
413
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
415
pxa2xx_mmci_write(opaque, offset, value);
418
static void pxa2xx_mmci_writeh(void *opaque,
419
hwaddr offset, uint32_t value)
421
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
423
pxa2xx_mmci_write(opaque, offset, value);
426
static void pxa2xx_mmci_writew(void *opaque,
427
hwaddr offset, uint32_t value)
429
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
431
pxa2xx_mmci_write(opaque, offset, value);
434
static const MemoryRegionOps pxa2xx_mmci_ops = {
436
.read = { pxa2xx_mmci_readb,
438
pxa2xx_mmci_readw, },
439
.write = { pxa2xx_mmci_writeb,
441
pxa2xx_mmci_writew, },
443
.endianness = DEVICE_NATIVE_ENDIAN,
446
static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
448
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
451
qemu_put_be32s(f, &s->status);
452
qemu_put_be32s(f, &s->clkrt);
453
qemu_put_be32s(f, &s->spi);
454
qemu_put_be32s(f, &s->cmdat);
455
qemu_put_be32s(f, &s->resp_tout);
456
qemu_put_be32s(f, &s->read_tout);
457
qemu_put_be32(f, s->blklen);
458
qemu_put_be32(f, s->numblk);
459
qemu_put_be32s(f, &s->intmask);
460
qemu_put_be32s(f, &s->intreq);
461
qemu_put_be32(f, s->cmd);
462
qemu_put_be32s(f, &s->arg);
463
qemu_put_be32(f, s->cmdreq);
464
qemu_put_be32(f, s->active);
465
qemu_put_be32(f, s->bytesleft);
467
qemu_put_byte(f, s->tx_len);
468
for (i = 0; i < s->tx_len; i ++)
469
qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
471
qemu_put_byte(f, s->rx_len);
472
for (i = 0; i < s->rx_len; i ++)
473
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
475
qemu_put_byte(f, s->resp_len);
476
for (i = s->resp_len; i < 9; i ++)
477
qemu_put_be16s(f, &s->resp_fifo[i]);
480
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
482
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
485
qemu_get_be32s(f, &s->status);
486
qemu_get_be32s(f, &s->clkrt);
487
qemu_get_be32s(f, &s->spi);
488
qemu_get_be32s(f, &s->cmdat);
489
qemu_get_be32s(f, &s->resp_tout);
490
qemu_get_be32s(f, &s->read_tout);
491
s->blklen = qemu_get_be32(f);
492
s->numblk = qemu_get_be32(f);
493
qemu_get_be32s(f, &s->intmask);
494
qemu_get_be32s(f, &s->intreq);
495
s->cmd = qemu_get_be32(f);
496
qemu_get_be32s(f, &s->arg);
497
s->cmdreq = qemu_get_be32(f);
498
s->active = qemu_get_be32(f);
499
s->bytesleft = qemu_get_be32(f);
501
s->tx_len = qemu_get_byte(f);
503
if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0)
505
for (i = 0; i < s->tx_len; i ++)
506
s->tx_fifo[i] = qemu_get_byte(f);
508
s->rx_len = qemu_get_byte(f);
510
if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0)
512
for (i = 0; i < s->rx_len; i ++)
513
s->rx_fifo[i] = qemu_get_byte(f);
515
s->resp_len = qemu_get_byte(f);
516
if (s->resp_len > 9 || s->resp_len < 0)
518
for (i = s->resp_len; i < 9; i ++)
519
qemu_get_be16s(f, &s->resp_fifo[i]);
524
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
526
BlockDriverState *bd, qemu_irq irq,
527
qemu_irq rx_dma, qemu_irq tx_dma)
531
s = (PXA2xxMMCIState *) g_malloc0(sizeof(PXA2xxMMCIState));
536
memory_region_init_io(&s->iomem, NULL, &pxa2xx_mmci_ops, s,
537
"pxa2xx-mmci", 0x00100000);
538
memory_region_add_subregion(sysmem, base, &s->iomem);
540
/* Instantiate the actual storage */
541
s->card = sd_init(bd, false);
543
register_savevm(NULL, "pxa2xx_mmci", 0, 0,
544
pxa2xx_mmci_save, pxa2xx_mmci_load, s);
549
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
550
qemu_irq coverswitch)
552
sd_set_cb(s->card, readonly, coverswitch);