58
* DBDMA control/status registers. All little-endian.
61
#define DBDMA_CONTROL 0x00
62
#define DBDMA_STATUS 0x01
63
#define DBDMA_CMDPTR_HI 0x02
64
#define DBDMA_CMDPTR_LO 0x03
65
#define DBDMA_INTR_SEL 0x04
66
#define DBDMA_BRANCH_SEL 0x05
67
#define DBDMA_WAIT_SEL 0x06
68
#define DBDMA_XFER_MODE 0x07
69
#define DBDMA_DATA2PTR_HI 0x08
70
#define DBDMA_DATA2PTR_LO 0x09
71
#define DBDMA_RES1 0x0A
72
#define DBDMA_ADDRESS_HI 0x0B
73
#define DBDMA_BRANCH_ADDR_HI 0x0C
74
#define DBDMA_RES2 0x0D
75
#define DBDMA_RES3 0x0E
76
#define DBDMA_RES4 0x0F
79
#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
81
#define DBDMA_CHANNEL_SHIFT 7
82
#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
84
#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
86
/* Bits in control and status registers */
95
#define DEVSTAT 0x00ff
98
* DBDMA command structure. These fields are all little-endian!
101
typedef struct dbdma_cmd {
102
uint16_t req_count; /* requested byte transfer count */
103
uint16_t command; /* command word (has bit-fields) */
104
uint32_t phy_addr; /* physical data address */
105
uint32_t cmd_dep; /* command-dependent field */
106
uint16_t res_count; /* residual count after completion */
107
uint16_t xfer_status; /* transfer status */
110
/* DBDMA command values in command field */
112
#define COMMAND_MASK 0xf000
113
#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
114
#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
115
#define INPUT_MORE 0x2000 /* transfer stream data to memory */
116
#define INPUT_LAST 0x3000 /* ditto, expect end marker */
117
#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
118
#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
119
#define DBDMA_NOP 0x6000 /* do nothing */
120
#define DBDMA_STOP 0x7000 /* suspend processing */
122
/* Key values in command field */
124
#define KEY_MASK 0x0700
125
#define KEY_STREAM0 0x0000 /* usual data stream */
126
#define KEY_STREAM1 0x0100 /* control/status stream */
127
#define KEY_STREAM2 0x0200 /* device-dependent stream */
128
#define KEY_STREAM3 0x0300 /* device-dependent stream */
129
#define KEY_STREAM4 0x0400 /* reserved */
130
#define KEY_REGS 0x0500 /* device register space */
131
#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
132
#define KEY_DEVICE 0x0700 /* device memory-mapped space */
134
/* Interrupt control values in command field */
136
#define INTR_MASK 0x0030
137
#define INTR_NEVER 0x0000 /* don't interrupt */
138
#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
139
#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
140
#define INTR_ALWAYS 0x0030 /* always interrupt */
142
/* Branch control values in command field */
144
#define BR_MASK 0x000c
145
#define BR_NEVER 0x0000 /* don't branch */
146
#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
147
#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
148
#define BR_ALWAYS 0x000c /* always branch */
150
/* Wait control values in command field */
152
#define WAIT_MASK 0x0003
153
#define WAIT_NEVER 0x0000 /* don't wait */
154
#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
155
#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
156
#define WAIT_ALWAYS 0x0003 /* always wait */
158
typedef struct DBDMA_channel {
160
uint32_t regs[DBDMA_REGS];
171
DBDMA_channel channels[DBDMA_CHANNELS];
57
static DBDMAState *dbdma_from_ch(DBDMA_channel *ch)
59
return container_of(ch, DBDMAState, channels[ch->channel]);
174
62
#ifdef DEBUG_DBDMA
175
63
static void dump_dbdma_cmd(dbdma_cmd *cmd)
579
476
case OUTPUT_MORE:
580
477
start_output(ch, key, phy_addr, req_count, 0);
583
480
case OUTPUT_LAST:
584
481
start_output(ch, key, phy_addr, req_count, 1);
588
485
start_input(ch, key, phy_addr, req_count, 0);
592
489
start_input(ch, key, phy_addr, req_count, 1);
596
493
if (key < KEY_REGS) {
712
616
DBDMA_channel *ch = &s->channels[channel];
713
617
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
715
DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
619
DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n",
716
621
DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
717
622
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
719
/* cmdptr cannot be modified if channel is RUN or ACTIVE */
624
/* cmdptr cannot be modified if channel is ACTIVE */
721
if (reg == DBDMA_CMDPTR_LO &&
722
(ch->regs[DBDMA_STATUS] & (RUN | ACTIVE)))
626
if (reg == DBDMA_CMDPTR_LO && (ch->regs[DBDMA_STATUS] & ACTIVE)) {
725
630
ch->regs[reg] = value;
849
754
s = g_malloc0(sizeof(DBDMAState));
851
memory_region_init_io(&s->mem, &dbdma_ops, s, "dbdma", 0x1000);
756
memory_region_init_io(&s->mem, NULL, &dbdma_ops, s, "dbdma", 0x1000);
852
757
*dbdma_mem = &s->mem;
853
758
vmstate_register(NULL, -1, &vmstate_dbdma, s);
854
759
qemu_register_reset(dbdma_reset, s);
856
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
761
s->bh = qemu_bh_new(DBDMA_run_bh, s);