483
485
return put_packet_binary(s, buf, strlen(buf));
486
/* The GDB remote protocol transfers values in target byte order. This means
487
we can use the raw memory access routines to access the value buffer.
488
Conveniently, these also handle the case where the buffer is mis-aligned.
490
#define GET_REG8(val) do { \
491
stb_p(mem_buf, val); \
494
#define GET_REG16(val) do { \
495
stw_p(mem_buf, val); \
498
#define GET_REG32(val) do { \
499
stl_p(mem_buf, val); \
502
#define GET_REG64(val) do { \
503
stq_p(mem_buf, val); \
507
#if TARGET_LONG_BITS == 64
508
#define GET_REGL(val) GET_REG64(val)
509
#define ldtul_p(addr) ldq_p(addr)
511
#define GET_REGL(val) GET_REG32(val)
512
#define ldtul_p(addr) ldl_p(addr)
515
#if defined(TARGET_I386)
518
static const int gpr_map[16] = {
519
R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
520
8, 9, 10, 11, 12, 13, 14, 15
523
#define gpr_map gpr_map32
525
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
527
#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
529
#define IDX_IP_REG CPU_NB_REGS
530
#define IDX_FLAGS_REG (IDX_IP_REG + 1)
531
#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
532
#define IDX_FP_REGS (IDX_SEG_REGS + 6)
533
#define IDX_XMM_REGS (IDX_FP_REGS + 16)
534
#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
536
static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
538
if (n < CPU_NB_REGS) {
539
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
540
GET_REG64(env->regs[gpr_map[n]]);
541
} else if (n < CPU_NB_REGS32) {
542
GET_REG32(env->regs[gpr_map32[n]]);
544
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
545
#ifdef USE_X86LDOUBLE
546
/* FIXME: byteswap float values - after fixing fpregs layout. */
547
memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
549
memset(mem_buf, 0, 10);
552
} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
554
if (n < CPU_NB_REGS32 ||
555
(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
556
stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
557
stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
563
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
568
case IDX_FLAGS_REG: GET_REG32(env->eflags);
570
case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
571
case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
572
case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
573
case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
574
case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
575
case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
577
case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
578
case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
579
(env->fpstt & 0x7) << 11);
580
case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
581
case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
582
case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
583
case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
584
case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
585
case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
587
case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
593
static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
595
uint16_t selector = ldl_p(mem_buf);
597
if (selector != env->segs[sreg].selector) {
598
#if defined(CONFIG_USER_ONLY)
599
cpu_x86_load_seg(env, sreg, selector);
601
unsigned int limit, flags;
604
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
605
base = selector << 4;
609
if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
612
cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
618
static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
622
if (n < CPU_NB_REGS) {
623
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
624
env->regs[gpr_map[n]] = ldtul_p(mem_buf);
625
return sizeof(target_ulong);
626
} else if (n < CPU_NB_REGS32) {
628
env->regs[n] &= ~0xffffffffUL;
629
env->regs[n] |= (uint32_t)ldl_p(mem_buf);
632
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
633
#ifdef USE_X86LDOUBLE
634
/* FIXME: byteswap float values - after fixing fpregs layout. */
635
memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
638
} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
640
if (n < CPU_NB_REGS32 ||
641
(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
642
env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
643
env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
649
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
650
env->eip = ldq_p(mem_buf);
653
env->eip &= ~0xffffffffUL;
654
env->eip |= (uint32_t)ldl_p(mem_buf);
658
env->eflags = ldl_p(mem_buf);
661
case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
662
case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
663
case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
664
case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
665
case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
666
case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
668
case IDX_FP_REGS + 8:
669
env->fpuc = ldl_p(mem_buf);
671
case IDX_FP_REGS + 9:
672
tmp = ldl_p(mem_buf);
673
env->fpstt = (tmp >> 11) & 7;
674
env->fpus = tmp & ~0x3800;
676
case IDX_FP_REGS + 10: /* ftag */ return 4;
677
case IDX_FP_REGS + 11: /* fiseg */ return 4;
678
case IDX_FP_REGS + 12: /* fioff */ return 4;
679
case IDX_FP_REGS + 13: /* foseg */ return 4;
680
case IDX_FP_REGS + 14: /* fooff */ return 4;
681
case IDX_FP_REGS + 15: /* fop */ return 4;
684
env->mxcsr = ldl_p(mem_buf);
688
/* Unrecognised register. */
692
#elif defined (TARGET_PPC)
694
/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
695
expects whatever the target description contains. Due to a
696
historical mishap the FP registers appear in between core integer
697
regs and PC, MSR, CR, and so forth. We hack round this by giving the
698
FP regs zero size when talking to a newer gdb. */
699
#define NUM_CORE_REGS 71
700
#if defined (TARGET_PPC64)
701
#define GDB_CORE_XML "power64-core.xml"
703
#define GDB_CORE_XML "power-core.xml"
706
static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
710
GET_REGL(env->gpr[n]);
715
stfq_p(mem_buf, env->fpr[n-32]);
719
case 64: GET_REGL(env->nip);
720
case 65: GET_REGL(env->msr);
725
for (i = 0; i < 8; i++)
726
cr |= env->crf[i] << (32 - ((i + 1) * 4));
729
case 67: GET_REGL(env->lr);
730
case 68: GET_REGL(env->ctr);
731
case 69: GET_REGL(env->xer);
736
GET_REG32(env->fpscr);
743
static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
747
env->gpr[n] = ldtul_p(mem_buf);
748
return sizeof(target_ulong);
753
env->fpr[n-32] = ldfq_p(mem_buf);
758
env->nip = ldtul_p(mem_buf);
759
return sizeof(target_ulong);
761
ppc_store_msr(env, ldtul_p(mem_buf));
762
return sizeof(target_ulong);
765
uint32_t cr = ldl_p(mem_buf);
767
for (i = 0; i < 8; i++)
768
env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
772
env->lr = ldtul_p(mem_buf);
773
return sizeof(target_ulong);
775
env->ctr = ldtul_p(mem_buf);
776
return sizeof(target_ulong);
778
env->xer = ldtul_p(mem_buf);
779
return sizeof(target_ulong);
784
store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
785
return sizeof(target_ulong);
791
#elif defined (TARGET_SPARC)
793
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
794
#define NUM_CORE_REGS 86
796
#define NUM_CORE_REGS 72
800
#define GET_REGA(val) GET_REG32(val)
802
#define GET_REGA(val) GET_REGL(val)
805
static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
809
GET_REGA(env->gregs[n]);
812
/* register window */
813
GET_REGA(env->regwptr[n - 8]);
815
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
819
GET_REG32(env->fpr[(n - 32) / 2].l.lower);
821
GET_REG32(env->fpr[(n - 32) / 2].l.upper);
824
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
826
case 64: GET_REGA(env->y);
827
case 65: GET_REGA(cpu_get_psr(env));
828
case 66: GET_REGA(env->wim);
829
case 67: GET_REGA(env->tbr);
830
case 68: GET_REGA(env->pc);
831
case 69: GET_REGA(env->npc);
832
case 70: GET_REGA(env->fsr);
833
case 71: GET_REGA(0); /* csr */
834
default: GET_REGA(0);
840
GET_REG32(env->fpr[(n - 32) / 2].l.lower);
842
GET_REG32(env->fpr[(n - 32) / 2].l.upper);
846
/* f32-f62 (double width, even numbers only) */
847
GET_REG64(env->fpr[(n - 32) / 2].ll);
850
case 80: GET_REGL(env->pc);
851
case 81: GET_REGL(env->npc);
852
case 82: GET_REGL((cpu_get_ccr(env) << 32) |
853
((env->asi & 0xff) << 24) |
854
((env->pstate & 0xfff) << 8) |
856
case 83: GET_REGL(env->fsr);
857
case 84: GET_REGL(env->fprs);
858
case 85: GET_REGL(env->y);
864
static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
866
#if defined(TARGET_ABI32)
869
tmp = ldl_p(mem_buf);
873
tmp = ldtul_p(mem_buf);
880
/* register window */
881
env->regwptr[n - 8] = tmp;
883
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
888
env->fpr[(n - 32) / 2].l.lower = tmp;
890
env->fpr[(n - 32) / 2].l.upper = tmp;
893
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
895
case 64: env->y = tmp; break;
896
case 65: cpu_put_psr(env, tmp); break;
897
case 66: env->wim = tmp; break;
898
case 67: env->tbr = tmp; break;
899
case 68: env->pc = tmp; break;
900
case 69: env->npc = tmp; break;
901
case 70: env->fsr = tmp; break;
909
tmp = ldl_p(mem_buf);
911
env->fpr[(n - 32) / 2].l.lower = tmp;
913
env->fpr[(n - 32) / 2].l.upper = tmp;
917
/* f32-f62 (double width, even numbers only) */
918
env->fpr[(n - 32) / 2].ll = tmp;
921
case 80: env->pc = tmp; break;
922
case 81: env->npc = tmp; break;
924
cpu_put_ccr(env, tmp >> 32);
925
env->asi = (tmp >> 24) & 0xff;
926
env->pstate = (tmp >> 8) & 0xfff;
927
cpu_put_cwp64(env, tmp & 0xff);
929
case 83: env->fsr = tmp; break;
930
case 84: env->fprs = tmp; break;
931
case 85: env->y = tmp; break;
938
#elif defined (TARGET_ARM)
940
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
941
whatever the target description contains. Due to a historical mishap
942
the FPA registers appear in between core integer regs and the CPSR.
943
We hack round this by giving the FPA regs zero size when talking to a
945
#define NUM_CORE_REGS 26
946
#define GDB_CORE_XML "arm-core.xml"
948
static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
951
/* Core integer register. */
952
GET_REG32(env->regs[n]);
958
memset(mem_buf, 0, 12);
963
/* FPA status register. */
969
GET_REG32(cpsr_read(env));
971
/* Unknown register. */
975
static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
979
tmp = ldl_p(mem_buf);
981
/* Mask out low bit of PC to workaround gdb bugs. This will probably
982
cause problems if we ever implement the Jazelle DBX extensions. */
987
/* Core integer register. */
991
if (n < 24) { /* 16-23 */
992
/* FPA registers (ignored). */
999
/* FPA status register (ignored). */
1005
cpsr_write (env, tmp, 0xffffffff);
1008
/* Unknown register. */
1012
#elif defined (TARGET_M68K)
1014
#define NUM_CORE_REGS 18
1016
#define GDB_CORE_XML "cf-core.xml"
1018
static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
1022
GET_REG32(env->dregs[n]);
1023
} else if (n < 16) {
1025
GET_REG32(env->aregs[n - 8]);
1028
case 16: GET_REG32(env->sr);
1029
case 17: GET_REG32(env->pc);
1032
/* FP registers not included here because they vary between
1033
ColdFire and m68k. Use XML bits for these. */
1037
static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
1041
tmp = ldl_p(mem_buf);
1045
env->dregs[n] = tmp;
1046
} else if (n < 16) {
1048
env->aregs[n - 8] = tmp;
1051
case 16: env->sr = tmp; break;
1052
case 17: env->pc = tmp; break;
1058
#elif defined (TARGET_MIPS)
1060
#define NUM_CORE_REGS 73
1062
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
1065
GET_REGL(env->active_tc.gpr[n]);
1067
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1068
if (n >= 38 && n < 70) {
1069
if (env->CP0_Status & (1 << CP0St_FR))
1070
GET_REGL(env->active_fpu.fpr[n - 38].d);
1072
GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1075
case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1076
case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1080
case 32: GET_REGL((int32_t)env->CP0_Status);
1081
case 33: GET_REGL(env->active_tc.LO[0]);
1082
case 34: GET_REGL(env->active_tc.HI[0]);
1083
case 35: GET_REGL(env->CP0_BadVAddr);
1084
case 36: GET_REGL((int32_t)env->CP0_Cause);
1085
case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1086
case 72: GET_REGL(0); /* fp */
1087
case 89: GET_REGL((int32_t)env->CP0_PRid);
1089
if (n >= 73 && n <= 88) {
1090
/* 16 embedded regs. */
1097
/* convert MIPS rounding mode in FCR31 to IEEE library */
1098
static unsigned int ieee_rm[] =
1100
float_round_nearest_even,
1101
float_round_to_zero,
1105
#define RESTORE_ROUNDING_MODE \
1106
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1108
static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
1112
tmp = ldtul_p(mem_buf);
1115
env->active_tc.gpr[n] = tmp;
1116
return sizeof(target_ulong);
1118
if (env->CP0_Config1 & (1 << CP0C1_FP)
1119
&& n >= 38 && n < 73) {
1121
if (env->CP0_Status & (1 << CP0St_FR))
1122
env->active_fpu.fpr[n - 38].d = tmp;
1124
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1128
env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1129
/* set rounding mode */
1130
RESTORE_ROUNDING_MODE;
1132
case 71: env->active_fpu.fcr0 = tmp; break;
1134
return sizeof(target_ulong);
1137
case 32: env->CP0_Status = tmp; break;
1138
case 33: env->active_tc.LO[0] = tmp; break;
1139
case 34: env->active_tc.HI[0] = tmp; break;
1140
case 35: env->CP0_BadVAddr = tmp; break;
1141
case 36: env->CP0_Cause = tmp; break;
1143
env->active_tc.PC = tmp & ~(target_ulong)1;
1145
env->hflags |= MIPS_HFLAG_M16;
1147
env->hflags &= ~(MIPS_HFLAG_M16);
1150
case 72: /* fp, ignored */ break;
1154
/* Other registers are readonly. Ignore writes. */
1158
return sizeof(target_ulong);
1160
#elif defined(TARGET_OPENRISC)
1162
#define NUM_CORE_REGS (32 + 3)
1164
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
1167
GET_REG32(env->gpr[n]);
1171
GET_REG32(env->ppc);
1175
GET_REG32(env->npc);
1189
static int cpu_gdb_write_register(CPUOpenRISCState *env,
1190
uint8_t *mem_buf, int n)
1194
if (n > NUM_CORE_REGS) {
1198
tmp = ldl_p(mem_buf);
1222
#elif defined (TARGET_SH4)
1224
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1225
/* FIXME: We should use XML for this. */
1227
#define NUM_CORE_REGS 59
1229
static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
1233
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1234
GET_REGL(env->gregs[n + 16]);
1236
GET_REGL(env->gregs[n]);
1239
GET_REGL(env->gregs[n]);
1249
GET_REGL(env->mach);
1251
GET_REGL(env->macl);
1255
GET_REGL(env->fpul);
1257
GET_REGL(env->fpscr);
1259
if (env->fpscr & FPSCR_FR) {
1260
stfl_p(mem_buf, env->fregs[n - 9]);
1262
stfl_p(mem_buf, env->fregs[n - 25]);
1270
GET_REGL(env->gregs[n - 43]);
1272
GET_REGL(env->gregs[n - (51 - 16)]);
1278
static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
1282
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1283
env->gregs[n + 16] = ldl_p(mem_buf);
1285
env->gregs[n] = ldl_p(mem_buf);
1289
env->gregs[n] = ldl_p(mem_buf);
1292
env->pc = ldl_p(mem_buf);
1295
env->pr = ldl_p(mem_buf);
1298
env->gbr = ldl_p(mem_buf);
1301
env->vbr = ldl_p(mem_buf);
1304
env->mach = ldl_p(mem_buf);
1307
env->macl = ldl_p(mem_buf);
1310
env->sr = ldl_p(mem_buf);
1313
env->fpul = ldl_p(mem_buf);
1316
env->fpscr = ldl_p(mem_buf);
1319
if (env->fpscr & FPSCR_FR) {
1320
env->fregs[n - 9] = ldfl_p(mem_buf);
1322
env->fregs[n - 25] = ldfl_p(mem_buf);
1326
env->ssr = ldl_p(mem_buf);
1329
env->spc = ldl_p(mem_buf);
1332
env->gregs[n - 43] = ldl_p(mem_buf);
1335
env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
1342
#elif defined (TARGET_MICROBLAZE)
1344
#define NUM_CORE_REGS (32 + 5)
1346
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
1349
GET_REG32(env->regs[n]);
1351
GET_REG32(env->sregs[n - 32]);
1356
static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
1360
if (n > NUM_CORE_REGS)
1363
tmp = ldl_p(mem_buf);
1368
env->sregs[n - 32] = tmp;
1372
#elif defined (TARGET_CRIS)
1374
#define NUM_CORE_REGS 49
1377
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
1380
GET_REG32(env->regs[n]);
1390
GET_REG8(env->pregs[n - 16]);
1393
GET_REG8(env->pregs[n - 16]);
1397
GET_REG16(env->pregs[n - 16]);
1401
GET_REG32(env->pregs[n - 16]);
1409
static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
1413
if (env->pregs[PR_VR] < 32)
1414
return read_register_crisv10(env, mem_buf, n);
1416
srs = env->pregs[PR_SRS];
1418
GET_REG32(env->regs[n]);
1421
if (n >= 21 && n < 32) {
1422
GET_REG32(env->pregs[n - 16]);
1424
if (n >= 33 && n < 49) {
1425
GET_REG32(env->sregs[srs][n - 33]);
1428
case 16: GET_REG8(env->pregs[0]);
1429
case 17: GET_REG8(env->pregs[1]);
1430
case 18: GET_REG32(env->pregs[2]);
1431
case 19: GET_REG8(srs);
1432
case 20: GET_REG16(env->pregs[4]);
1433
case 32: GET_REG32(env->pc);
1439
static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
1446
tmp = ldl_p(mem_buf);
1452
if (n >= 21 && n < 32) {
1453
env->pregs[n - 16] = tmp;
1456
/* FIXME: Should support function regs be writable? */
1460
case 18: env->pregs[PR_PID] = tmp; break;
1463
case 32: env->pc = tmp; break;
1468
#elif defined (TARGET_ALPHA)
1470
#define NUM_CORE_REGS 67
1472
static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
1482
d.d = env->fir[n - 32];
1486
val = cpu_alpha_load_fpcr(env);
1496
/* 31 really is the zero register; 65 is unassigned in the
1497
gdb protocol, but is still required to occupy 8 bytes. */
1506
static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
1508
target_ulong tmp = ldtul_p(mem_buf);
1517
env->fir[n - 32] = d.d;
1520
cpu_alpha_store_fpcr(env, tmp);
1530
/* 31 really is the zero register; 65 is unassigned in the
1531
gdb protocol, but is still required to occupy 8 bytes. */
1538
#elif defined (TARGET_S390X)
1540
#define NUM_CORE_REGS S390_NUM_REGS
1542
static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
1548
case S390_PSWM_REGNUM:
1549
cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
1550
val = deposit64(env->psw.mask, 44, 2, cc_op);
1553
case S390_PSWA_REGNUM:
1554
GET_REGL(env->psw.addr);
1556
case S390_R0_REGNUM ... S390_R15_REGNUM:
1557
GET_REGL(env->regs[n-S390_R0_REGNUM]);
1559
case S390_A0_REGNUM ... S390_A15_REGNUM:
1560
GET_REG32(env->aregs[n-S390_A0_REGNUM]);
1562
case S390_FPC_REGNUM:
1563
GET_REG32(env->fpc);
1565
case S390_F0_REGNUM ... S390_F15_REGNUM:
1566
GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
1573
static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
1578
tmpl = ldtul_p(mem_buf);
1579
tmp32 = ldl_p(mem_buf);
1582
case S390_PSWM_REGNUM:
1583
env->psw.mask = tmpl;
1584
env->cc_op = extract64(tmpl, 44, 2);
1586
case S390_PSWA_REGNUM:
1587
env->psw.addr = tmpl;
1589
case S390_R0_REGNUM ... S390_R15_REGNUM:
1590
env->regs[n-S390_R0_REGNUM] = tmpl;
1592
case S390_A0_REGNUM ... S390_A15_REGNUM:
1593
env->aregs[n-S390_A0_REGNUM] = tmp32;
1596
case S390_FPC_REGNUM:
1600
case S390_F0_REGNUM ... S390_F15_REGNUM:
1601
env->fregs[n-S390_F0_REGNUM].ll = tmpl;
1608
#elif defined (TARGET_LM32)
1610
#include "hw/lm32/lm32_pic.h"
1611
#define NUM_CORE_REGS (32 + 7)
1613
static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
1616
GET_REG32(env->regs[n]);
1622
/* FIXME: put in right exception ID */
1627
GET_REG32(env->eba);
1630
GET_REG32(env->deba);
1636
GET_REG32(lm32_pic_get_im(env->pic_state));
1639
GET_REG32(lm32_pic_get_ip(env->pic_state));
1646
static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
1650
if (n > NUM_CORE_REGS) {
1654
tmp = ldl_p(mem_buf);
1673
lm32_pic_set_im(env->pic_state, tmp);
1676
lm32_pic_set_ip(env->pic_state, tmp);
1682
#elif defined(TARGET_XTENSA)
1684
/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
1685
* Use num_regs to see all registers. gdb modification is required for that:
1686
* reset bit 0 in the 'flags' field of the registers definitions in the
1687
* gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
1689
#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
1690
#define num_g_regs NUM_CORE_REGS
1692
static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
1694
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1696
if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1700
switch (reg->type) {
1706
xtensa_sync_phys_from_window(env);
1707
GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
1711
GET_REG32(env->sregs[reg->targno & 0xff]);
1715
GET_REG32(env->uregs[reg->targno & 0xff]);
1719
GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
1723
GET_REG32(env->regs[reg->targno & 0x0f]);
1727
qemu_log("%s from reg %d of unsupported type %d\n",
1728
__func__, n, reg->type);
1733
static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
1736
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1738
if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1742
tmp = ldl_p(mem_buf);
1744
switch (reg->type) {
1750
env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
1751
xtensa_sync_window_from_phys(env);
1755
env->sregs[reg->targno & 0xff] = tmp;
1759
env->uregs[reg->targno & 0xff] = tmp;
1763
env->fregs[reg->targno & 0x0f] = make_float32(tmp);
1767
env->regs[reg->targno & 0x0f] = tmp;
1771
qemu_log("%s to reg %d of unsupported type %d\n",
1772
__func__, n, reg->type);
1780
#define NUM_CORE_REGS 0
1782
static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
1787
static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
1794
#if !defined(TARGET_XTENSA)
1795
static int num_g_regs = NUM_CORE_REGS;
1799
488
/* Encode data using the encoding for 'x' packets. */
1800
489
static int memtox(char *buf, const char *mem, int len)