2
* TI OMAP processors UART emulation.
4
* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5
* Copyright (C) 2007-2009 Nokia Corporation
7
* This program is free software; you can redistribute it and/or
8
* modify it under the terms of the GNU General Public License as
9
* published by the Free Software Foundation; either version 2 or
10
* (at your option) version 3 of the License.
12
* This program is distributed in the hope that it will be useful,
13
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
* GNU General Public License for more details.
17
* You should have received a copy of the GNU General Public License along
18
* with this program; if not, see <http://www.gnu.org/licenses/>.
20
#include "sysemu/char.h"
22
#include "hw/arm/omap.h"
23
#include "hw/char/serial.h"
24
#include "exec/address-spaces.h"
25
#include "hw/sysbus.h"
27
/* The OMAP UART functionality is similar to the TI16C752; it is
28
* an enhanced version of the 16550A and we piggy-back on the 16550
31
* Currently unmodelled functionality:
32
* + We should have a 64 byte FIFO but QEMU's SerialState emulation
33
* always uses a 16 byte FIFO
35
* + interrupts based on TCR/TLR values
36
* + XON/XOFF flow control
37
* + UASR auto-baudrate-detection
44
SerialState *serial; /* TODO */
45
const MemoryRegionOps *serial_ops;
66
uint8_t xon[2], xoff[2];
69
static void omap_uart_reset(DeviceState *qdev)
71
struct omap_uart_s *s = FROM_SYSBUS(struct omap_uart_s,
72
SYS_BUS_DEVICE(qdev));
86
s->xon[0] = s->xon[1] = 0;
87
s->xoff[0] = s->xoff[1] = 0;
90
static uint64_t omap_uart_read(void *opaque, hwaddr addr,
93
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
99
return s->serial_ops->read(s->serial, addr, size);
101
if (s->lcr_cache == 0xbf) {
104
return s->serial_ops->read(s->serial, addr, size);
107
if (s->lcr_cache == 0xbf) {
108
return s->xon[(addr & 7) >> 2];
109
} else if (addr == 0x10) {
110
return s->serial_ops->read(s->serial, addr, size)
111
| (s->mcr_cache & 0xe0);
113
return s->serial_ops->read(s->serial, addr, size);
116
if ((s->efr & 0x10) && (s->mcr_cache & 0x40)) {
117
return (addr == 0x18) ? s->tcr : s->tlr;
119
if (s->lcr_cache == 0xbf) {
120
return s->xoff[(addr & 7) >> 2];
122
return s->serial_ops->read(s->serial, addr, size);
123
case 0x20: /* MDR1 */
125
case 0x24: /* MDR2 */
127
case 0x28: /* SFLSR */
129
case 0x2c: /* RESUME */
131
case 0x30: /* SFREGL */
133
case 0x34: /* SFREGH */
135
case 0x38: /* UASR/BLR */
136
if ((s->lcr_cache & 0x80)) {
137
return 0; /* FIXME: return correct autodetect value */
140
case 0x3c: /* ACREG */
141
return (s->lcr_cache & 0x80) ? 0 : s->acreg;
146
case 0x48: /* EBLR (OMAP2) */
148
case 0x4C: /* OSC_12M_SEL (OMAP1) */
152
case 0x54: /* SYSC (OMAP2) */
153
return s->syscontrol;
154
case 0x58: /* SYSS (OMAP2) */
156
case 0x5c: /* WER (OMAP2) */
158
case 0x60: /* CFPS (OMAP2) */
166
static void omap_uart_write(void *opaque, hwaddr addr,
167
uint64_t value, unsigned size)
169
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
174
s->serial_ops->write(s->serial, addr, value, size);
177
if (s->lcr_cache == 0xbf) {
180
s->serial_ops->write(s->serial, addr, value, size);
184
s->lcr_cache = value;
185
s->serial_ops->write(s->serial, addr, value, size);
189
if (s->lcr_cache == 0xbf) {
190
s->xon[(addr & 7) >> 2] = value;
193
s->mcr_cache = value & 0x7f;
195
s->serial_ops->write(s->serial, addr, value, size);
200
if ((s->efr & 0x10) && (s->mcr_cache & 0x40)) {
202
s->tcr = value & 0xff;
204
s->tlr = value & 0xff;
206
} else if (s->lcr_cache == 0xbf) {
207
s->xoff[(addr & 7) >> 2] = value;
209
s->serial_ops->write(s->serial, addr, value, size);
212
case 0x20: /* MDR1 */
213
s->mdr[0] = value & 0x7f;
215
case 0x24: /* MDR2 */
216
s->mdr[1] = value & 0xff;
218
case 0x28: /* TXFLL */
219
case 0x2c: /* TXFLH */
220
case 0x30: /* RXFLL */
221
case 0x34: /* RXFLH */
225
if (!(s->lcr_cache & 0x80)) {
226
s->blr = value & 0xc0;
229
case 0x3c: /* ACREG */
230
if (!(s->lcr_cache & 0x80)) {
231
s->acreg = value & 0xff;
235
s->scr = value & 0xff;
240
case 0x48: /* EBLR (OMAP2) */
241
s->eblr = value & 0xff;
243
case 0x4C: /* OSC_12M_SEL (OMAP1) */
244
s->clksel = value & 1;
249
case 0x54: /* SYSC (OMAP2) */
250
s->syscontrol = value & 0x1d;
252
/* TODO: reset s->serial also. */
253
omap_uart_reset(&s->busdev.qdev);
256
case 0x58: /* SYSS (OMAP2) */
259
case 0x5c: /* WER (OMAP2) */
260
s->wkup = value & 0x7f;
262
case 0x60: /* CFPS (OMAP2) */
263
s->cfps = value & 0xff;
270
static const MemoryRegionOps omap_uart_ops = {
271
.read = omap_uart_read,
272
.write = omap_uart_write,
273
.endianness = DEVICE_NATIVE_ENDIAN,
276
static int omap_uart_init(SysBusDevice *busdev)
278
struct omap_uart_s *s = FROM_SYSBUS(struct omap_uart_s, busdev);
280
s->chr = qemu_chr_new(busdev->qdev.id, "null", NULL);
282
/* TODO: DMA support. Current 16550A emulation does not emulate DMA mode
283
* transfers via TXRDY/RXRDY pins. We create DMA irq lines here for
284
* future use nevertheless. */
285
/* Nasty hackery because trying to extend an existing device is
286
* not really supported, and the serial driver isn't even qdev.
288
s->serial = serial_mm_init(NULL, 0, 2, NULL, s->baudrate, s->chr,
289
DEVICE_NATIVE_ENDIAN);
290
s->serial_ops = serial_get_memops(DEVICE_NATIVE_ENDIAN);
291
sysbus_init_irq(busdev, serial_get_irq(s->serial));
292
sysbus_init_irq(busdev, &s->tx_drq);
293
sysbus_init_irq(busdev, &s->rx_drq);
294
memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap_uart",
296
sysbus_init_mmio(busdev, &s->iomem);
300
static Property omap_uart_properties[] = {
301
DEFINE_PROP_UINT32("mmio_size", struct omap_uart_s, mmio_size, 0x400),
302
DEFINE_PROP_UINT32("baudrate", struct omap_uart_s, baudrate, 0),
303
DEFINE_PROP_CHR("chardev", struct omap_uart_s, chr),
304
DEFINE_PROP_END_OF_LIST()
307
static void omap_uart_class_init(ObjectClass *klass, void *data)
309
DeviceClass *dc = DEVICE_CLASS(klass);
310
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
311
k->init = omap_uart_init;
312
dc->props = omap_uart_properties;
313
dc->reset = omap_uart_reset;
316
static TypeInfo omap_uart_info = {
318
.parent = TYPE_SYS_BUS_DEVICE,
319
.instance_size = sizeof(struct omap_uart_s),
320
.class_init = omap_uart_class_init,
323
static void omap_uart_register_types(void)
325
type_register_static(&omap_uart_info);
328
void omap_uart_attach(DeviceState *qdev, CharDriverState *chr,
331
struct omap_uart_s *s = FROM_SYSBUS(struct omap_uart_s,
332
SYS_BUS_DEVICE(qdev));
333
s->chr = chr ?: qemu_chr_new(label, "null", NULL);
334
serial_change_char_driver(s->serial, s->chr);
337
type_init(omap_uart_register_types)