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#if !defined(__XICS_H__)
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#include "hw/sysbus.h"
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#define TYPE_XICS "xics"
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#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
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#define XICS_IPI 0x2
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#define XICS_IRQ_BASE 0x10
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qemu_irq xics_get_qirq(struct icp_state *icp, int irq);
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void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi);
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struct icp_state *xics_system_init(int nr_servers, int nr_irqs);
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void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu);
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#define XICS_IRQ_BASE (XICS_BUID << 12)
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* We currently only support one BUID which is our interrupt base
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* (the kernel implementation supports more but we don't exploit
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typedef struct XICSState XICSState;
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typedef struct ICPState ICPState;
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typedef struct ICSState ICSState;
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typedef struct ICSIRQState ICSIRQState;
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SysBusDevice parent_obj;
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#define TYPE_ICP "icp"
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#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
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DeviceState parent_obj;
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uint8_t pending_priority;
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#define TYPE_ICS "ics"
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#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
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DeviceState parent_obj;
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uint8_t saved_priority;
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#define XICS_STATUS_ASSERTED 0x1
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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qemu_irq xics_get_qirq(XICSState *icp, int irq);
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void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
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void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
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#endif /* __XICS_H__ */