153
static void cpu_pre_save(void *opaque)
155
ARMCPU *cpu = opaque;
158
if (!write_kvmstate_to_list(cpu)) {
159
/* This should never fail */
163
if (!write_cpustate_to_list(cpu)) {
164
/* This should never fail. */
169
cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
170
memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
171
cpu->cpreg_array_len * sizeof(uint64_t));
172
memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
173
cpu->cpreg_array_len * sizeof(uint64_t));
176
static int cpu_post_load(void *opaque, int version_id)
178
ARMCPU *cpu = opaque;
181
/* Update the values list from the incoming migration data.
182
* Anything in the incoming data which we don't know about is
183
* a migration failure; anything we know about but the incoming
184
* data doesn't specify retains its current (reset) value.
185
* The indexes list remains untouched -- we only inspect the
186
* incoming migration index list so we can match the values array
187
* entries with the right slots in our own values array.
190
for (i = 0, v = 0; i < cpu->cpreg_array_len
191
&& v < cpu->cpreg_vmstate_array_len; i++) {
192
if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
193
/* register in our list but not incoming : skip it */
196
if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
197
/* register in their list but not ours: fail migration */
200
/* matching register, copy the value over */
201
cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
206
if (!write_list_to_kvmstate(cpu)) {
209
/* Note that it's OK for the TCG side not to know about
210
* every register in the list; KVM is authoritative if
213
write_list_to_cpustate(cpu);
215
if (!write_list_to_cpustate(cpu)) {
151
223
const VMStateDescription vmstate_arm_cpu = {
154
.minimum_version_id = 12,
155
.minimum_version_id_old = 12,
226
.minimum_version_id = 13,
227
.minimum_version_id_old = 13,
228
.pre_save = cpu_pre_save,
229
.post_load = cpu_post_load,
156
230
.fields = (VMStateField[]) {
157
231
VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
169
243
VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 7),
170
244
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
171
245
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
172
VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
173
VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
174
VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
175
VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
176
VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
177
VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
178
VMSTATE_UINT32(env.cp15.c1_sedbg, ARMCPU),
179
VMSTATE_UINT32(env.cp15.c1_nseac, ARMCPU),
180
VMSTATE_UINT32(env.cp15.c2_base0, ARMCPU),
181
VMSTATE_UINT32(env.cp15.c2_base0_hi, ARMCPU),
182
VMSTATE_UINT32(env.cp15.c2_base1, ARMCPU),
183
VMSTATE_UINT32(env.cp15.c2_base1_hi, ARMCPU),
184
VMSTATE_UINT32(env.cp15.c2_control, ARMCPU),
185
VMSTATE_UINT32(env.cp15.c2_mask, ARMCPU),
186
VMSTATE_UINT32(env.cp15.c2_base_mask, ARMCPU),
187
VMSTATE_UINT32(env.cp15.c2_data, ARMCPU),
188
VMSTATE_UINT32(env.cp15.c2_insn, ARMCPU),
189
VMSTATE_UINT32(env.cp15.c3, ARMCPU),
190
VMSTATE_UINT32(env.cp15.c5_insn, ARMCPU),
191
VMSTATE_UINT32(env.cp15.c5_data, ARMCPU),
192
VMSTATE_UINT32_ARRAY(env.cp15.c6_region, ARMCPU, 8),
193
VMSTATE_UINT32(env.cp15.c6_insn, ARMCPU),
194
VMSTATE_UINT32(env.cp15.c6_data, ARMCPU),
195
VMSTATE_UINT32(env.cp15.c7_par, ARMCPU),
196
VMSTATE_UINT32(env.cp15.c7_par_hi, ARMCPU),
197
VMSTATE_UINT32(env.cp15.c9_insn, ARMCPU),
198
VMSTATE_UINT32(env.cp15.c9_data, ARMCPU),
199
VMSTATE_UINT32(env.cp15.c9_pmcr, ARMCPU),
200
VMSTATE_UINT32(env.cp15.c9_pmcnten, ARMCPU),
201
VMSTATE_UINT32(env.cp15.c9_pmovsr, ARMCPU),
202
VMSTATE_UINT32(env.cp15.c9_pmxevtyper, ARMCPU),
203
VMSTATE_UINT32(env.cp15.c9_pmuserenr, ARMCPU),
204
VMSTATE_UINT32(env.cp15.c9_pminten, ARMCPU),
205
VMSTATE_UINT32(env.cp15.c13_fcse, ARMCPU),
206
VMSTATE_UINT32(env.cp15.c13_context, ARMCPU),
207
VMSTATE_UINT32(env.cp15.c13_tls1, ARMCPU),
208
VMSTATE_UINT32(env.cp15.c13_tls2, ARMCPU),
209
VMSTATE_UINT32(env.cp15.c13_tls3, ARMCPU),
210
VMSTATE_UINT32(env.cp15.c15_cpar, ARMCPU),
211
VMSTATE_UINT32(env.cp15.c15_ticonfig, ARMCPU),
212
VMSTATE_UINT32(env.cp15.c15_i_max, ARMCPU),
213
VMSTATE_UINT32(env.cp15.c15_i_min, ARMCPU),
214
VMSTATE_UINT32(env.cp15.c15_threadid, ARMCPU),
215
VMSTATE_UINT32(env.cp15.c15_power_control, ARMCPU),
216
VMSTATE_UINT32(env.cp15.c15_diagnostic, ARMCPU),
217
VMSTATE_UINT32(env.cp15.c15_power_diagnostic, ARMCPU),
246
/* The length-check must come before the arrays to avoid
247
* incoming data possibly overflowing the array.
249
VMSTATE_INT32_LE(cpreg_vmstate_array_len, ARMCPU),
250
VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
251
cpreg_vmstate_array_len,
252
0, vmstate_info_uint64, uint64_t),
253
VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
254
cpreg_vmstate_array_len,
255
0, vmstate_info_uint64, uint64_t),
218
256
VMSTATE_UINT32(env.exclusive_addr, ARMCPU),
219
257
VMSTATE_UINT32(env.exclusive_val, ARMCPU),
220
258
VMSTATE_UINT32(env.exclusive_high, ARMCPU),
221
259
VMSTATE_UINT64(env.features, ARMCPU),
260
VMSTATE_TIMER(gt_timer[GTIMER_PHYS], ARMCPU),
261
VMSTATE_TIMER(gt_timer[GTIMER_VIRT], ARMCPU),
222
262
VMSTATE_END_OF_LIST()
224
264
.subsections = (VMStateSubsection[]) {