146
153
typedef struct _eeprom24c0x_t eeprom24c0x_t;
148
static eeprom24c0x_t eeprom = {
155
static eeprom24c0x_t spd_eeprom = {
150
/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
157
/* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
151
158
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
152
/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
153
/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
159
/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
160
/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
154
161
/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
155
162
/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
156
163
/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
169
static uint8_t eeprom24c0x_read(void)
176
static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
178
enum { SDR = 0x4, DDR2 = 0x8 } type;
179
uint8_t *spd = spd_eeprom.contents;
181
uint16_t density = 0;
184
/* work in terms of MB */
187
while ((ram_size >= 4) && (nbanks <= 2)) {
188
int sz_log2 = MIN(31 - clz32(ram_size), 14);
190
density |= 1 << (sz_log2 - 2);
191
ram_size -= 1 << sz_log2;
194
/* split to 2 banks if possible */
195
if ((nbanks == 1) && (density > 1)) {
200
if (density & 0xff00) {
201
density = (density & 0xe0) | ((density >> 8) & 0x1f);
203
} else if (!(density & 0x1f)) {
210
fprintf(stderr, "Warning: SPD cannot represent final %dMB"
211
" of SDRAM\n", (int)ram_size);
214
/* fill in SPD memory information */
221
for (i = 0; i < 63; i++) {
226
memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
229
static void generate_eeprom_serial(uint8_t *eeprom)
232
uint8_t mac[6] = { 0x00 };
233
uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
236
eeprom[pos++] = 0x01;
239
eeprom[pos++] = 0x02;
242
eeprom[pos++] = 0x01; /* MAC */
243
eeprom[pos++] = 0x06; /* length */
244
memcpy(&eeprom[pos], mac, sizeof(mac));
248
eeprom[pos++] = 0x02; /* serial */
249
eeprom[pos++] = 0x05; /* length */
250
memcpy(&eeprom[pos], sn, sizeof(sn));
255
for (i = 0; i < pos; i++) {
256
eeprom[pos] += eeprom[i];
260
static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
171
262
logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
172
eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
263
eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
176
static void eeprom24c0x_write(int scl, int sda)
267
static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
178
if (eeprom.scl && scl && (eeprom.sda != sda)) {
269
if (eeprom->scl && scl && (eeprom->sda != sda)) {
179
270
logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
180
eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
271
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
272
sda ? "stop" : "start");
185
} else if (eeprom.tick == 0 && !eeprom.ack) {
277
} else if (eeprom->tick == 0 && !eeprom->ack) {
186
278
/* Waiting for start. */
187
279
logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
188
eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
189
} else if (!eeprom.scl && scl) {
280
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
281
} else if (!eeprom->scl && scl) {
190
282
logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
191
eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
283
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
193
285
logout("\ti2c ack bit = 0\n");
196
} else if (eeprom.sda == sda) {
288
} else if (eeprom->sda == sda) {
197
289
uint8_t bit = (sda != 0);
198
290
logout("\ti2c bit = %d\n", bit);
199
if (eeprom.tick < 9) {
200
eeprom.command <<= 1;
201
eeprom.command += bit;
203
if (eeprom.tick == 9) {
204
logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
207
} else if (eeprom.tick < 17) {
208
if (eeprom.command & 1) {
209
sda = ((eeprom.data & 0x80) != 0);
211
eeprom.address <<= 1;
212
eeprom.address += bit;
215
if (eeprom.tick == 17) {
216
eeprom.data = eeprom.contents[eeprom.address];
217
logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
221
} else if (eeprom.tick >= 17) {
291
if (eeprom->tick < 9) {
292
eeprom->command <<= 1;
293
eeprom->command += bit;
295
if (eeprom->tick == 9) {
296
logout("\tcommand 0x%04x, %s\n", eeprom->command,
297
bit ? "read" : "write");
300
} else if (eeprom->tick < 17) {
301
if (eeprom->command & 1) {
302
sda = ((eeprom->data & 0x80) != 0);
304
eeprom->address <<= 1;
305
eeprom->address += bit;
308
if (eeprom->tick == 17) {
309
eeprom->data = eeprom->contents[eeprom->address];
310
logout("\taddress 0x%04x, data 0x%02x\n",
311
eeprom->address, eeprom->data);
315
} else if (eeprom->tick >= 17) {
225
319
logout("\tsda changed with raising scl\n");
228
logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
322
logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
323
scl, eeprom->sda, sda);
234
329
static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
930
/* Map the BIOS at a 2nd physical location, as on the real board. */
931
memory_region_init_alias(bios_alias, "bios.1fc", bios, 0, BIOS_SIZE);
932
memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_alias);
1041
* Map the BIOS at a 2nd physical location, as on the real board.
1042
* Copy it so that we can patch in the MIPS revision, which cannot be
1043
* handled by an overlapping region as the resulting ROM code subpage
1044
* regions are not executable.
1046
memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE);
1047
if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1048
FLASH_ADDRESS, BIOS_SIZE)) {
1049
memcpy(memory_region_get_ram_ptr(bios_copy),
1050
memory_region_get_ram_ptr(bios), BIOS_SIZE);
1052
memory_region_set_readonly(bios_copy, true);
1053
memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
934
/* Board ID = 0x420 (Malta Board with CoreLV)
935
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
936
map to the board ID. */
937
stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420);
1055
/* Board ID = 0x420 (Malta Board with CoreLV) */
1056
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
939
1058
/* Init internal devices */
940
1059
cpu_mips_irq_init_cpu(env);
966
1085
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
967
1086
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
968
1087
isa_get_irq(NULL, 9), NULL, 0, NULL);
969
/* TODO: Populate SPD eeprom data. */
970
smbus_eeprom_init(smbus, 8, NULL, 0);
1088
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1089
g_free(smbus_eeprom_buf);
971
1090
pit = pit_init(isa_bus, 0x40, 0, NULL);
972
1091
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
973
1092
DMA_init(0, cpu_exit_irq);