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Viewing changes to arch/arm/common/timer-sp.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/common/timer-sp.c
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
 
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
 
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/arm_timer.h>
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/*
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 * These timers are currently always setup to be clocked at 1MHz.
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 */
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#define TIMER_FREQ_KHZ  (1000)
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#define TIMER_RELOAD    (TIMER_FREQ_KHZ * 1000 / HZ)
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static void __iomem *clksrc_base;
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static cycle_t sp804_read(struct clocksource *cs)
 
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static long __init sp804_get_clock_rate(const char *name)
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{
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        return ~readl(clksrc_base + TIMER_VALUE);
 
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        struct clk *clk;
 
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        long rate;
 
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        int err;
 
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        clk = clk_get_sys("sp804", name);
 
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        if (IS_ERR(clk)) {
 
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                pr_err("sp804: %s clock not found: %d\n", name,
 
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                        (int)PTR_ERR(clk));
 
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                return PTR_ERR(clk);
 
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        }
 
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        err = clk_enable(clk);
 
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        if (err) {
 
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                pr_err("sp804: %s clock failed to enable: %d\n", name, err);
 
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                clk_put(clk);
 
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                return err;
 
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        }
 
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        rate = clk_get_rate(clk);
 
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        if (rate < 0) {
 
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                pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
 
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                clk_disable(clk);
 
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                clk_put(clk);
 
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        }
 
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        return rate;
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}
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static struct clocksource clocksource_sp804 = {
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        .name           = "timer3",
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        .rating         = 200,
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        .read           = sp804_read,
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        .mask           = CLOCKSOURCE_MASK(32),
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        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init sp804_clocksource_init(void __iomem *base)
 
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void __init sp804_clocksource_init(void __iomem *base, const char *name)
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{
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        struct clocksource *cs = &clocksource_sp804;
 
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        long rate = sp804_get_clock_rate(name);
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        clksrc_base = base;
 
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        if (rate < 0)
 
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                return;
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        /* setup timer 0 as free-running clocksource */
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        writel(0, clksrc_base + TIMER_CTRL);
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        writel(0xffffffff, clksrc_base + TIMER_LOAD);
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        writel(0xffffffff, clksrc_base + TIMER_VALUE);
 
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        writel(0, base + TIMER_CTRL);
 
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        writel(0xffffffff, base + TIMER_LOAD);
 
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        writel(0xffffffff, base + TIMER_VALUE);
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        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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                clksrc_base + TIMER_CTRL);
 
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                base + TIMER_CTRL);
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        clocksource_register_khz(cs, TIMER_FREQ_KHZ);
 
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        clocksource_mmio_init(base + TIMER_VALUE, name,
 
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                rate, 200, 32, clocksource_mmio_readl_down);
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}
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static void __iomem *clkevt_base;
 
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static unsigned long clkevt_reload;
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/*
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 * IRQ handler for the timer
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        switch (mode) {
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        case CLOCK_EVT_MODE_PERIODIC:
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                writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
 
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                writel(clkevt_reload, clkevt_base + TIMER_LOAD);
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                ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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                break;
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}
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static struct clock_event_device sp804_clockevent = {
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        .name           = "timer0",
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        .shift          = 32,
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        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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        .set_mode       = sp804_set_mode,
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        .dev_id         = &sp804_clockevent,
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};
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void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
 
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void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
 
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        const char *name)
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{
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        struct clock_event_device *evt = &sp804_clockevent;
 
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        long rate = sp804_get_clock_rate(name);
 
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        if (rate < 0)
 
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                return;
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        clkevt_base = base;
 
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        clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
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        evt->irq = timer_irq;
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        evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
 
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        evt->name = name;
 
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        evt->irq = irq;
 
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        evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift);
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        evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
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        evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
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        setup_irq(timer_irq, &sp804_timer_irq);
 
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        setup_irq(irq, &sp804_timer_irq);
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        clockevents_register_device(evt);
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}