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Viewing changes to drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
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/*
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 * For performance reasons, we handle storage endpoint transfers upto 4 KB
 
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 * For performance reasons, we handle storage endpoint transfers up to 4 KB
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 * within the HAL itself.
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 */
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 #define CYASSTORAGE_WRITE_EP_NUM       (4)
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                                ((ep) == 6) || ((ep) == 8))
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/*
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 * persistant, stores current GPMC interface cfg mode
 
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 * persistent, stores current GPMC interface cfg mode
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 */
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static uint8_t pnand_16bit;
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/*
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 * keep processing new WB DRQ in ISR untill all handled (performance feature)
 
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 * keep processing new WB DRQ in ISR until all handled (performance feature)
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 */
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#define PROCESS_MULTIPLE_DRQ_IN_ISR (1)
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         * dma_xfer_sz - size of the next dma xfer on P port
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         * seg_xfer_cnt -  counts xfered bytes for in current sg_list
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         *              memory segment
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         * req_xfer_cnt - total number of bytes transfered so far in
 
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         * req_xfer_cnt - total number of bytes transferred so far in
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         *              current request
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         * req_length - total request length
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         */
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        u32 tmp32;
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        int err;
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        struct gpmc_timings     timings;
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        /*
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         * get GPMC i/o registers base(already been i/o mapped
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         * in kernel, no need for separate i/o remap)
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         */
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        gpmc_base = phys_to_virt(OMAP34XX_GPMC_BASE);
 
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        gpmc_base = (u32)ioremap_nocache(OMAP34XX_GPMC_BASE, BLKSZ_4K);
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        DBGPRN(KERN_INFO "kernel has gpmc_base=%x , val@ the base=%x",
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                gpmc_base, __raw_readl(gpmc_base)
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        );
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        int result;
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        int irq_pin  = AST_INT;
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        set_irq_type(OMAP_GPIO_IRQ(irq_pin), IRQ_TYPE_LEVEL_LOW);
 
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        irq_set_irq_type(OMAP_GPIO_IRQ(irq_pin), IRQ_TYPE_LEVEL_LOW);
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        /*
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         * for shared IRQS must provide non NULL device ptr
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                cy_as_hal_print_message(KERN_INFO "%s virt_addr=%x\n",
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                                        gpio_vma_tab[i].name,
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                                        (u32)gpio_vma_tab[i].virt_addr);
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        };
 
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        }
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        /*
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         * force OMAP_GPIO_126  to rleased state,
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/*
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 * This function is expected to create a sleep channel.
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 * The data structure that represents the sleep channel object
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 * sleep channel (which is Linux "wait_queue_head_t wq" for this paticular HAL)
 
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 * sleep channel (which is Linux "wait_queue_head_t wq" for this particular HAL)
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 * passed as a pointer, and allpocated by the caller
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 * (typically as a local var on the stack) "Create" word should read as
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 * "SleepOn", this func doesn't actually create anything
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         */
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        cy_as_hal_gpmc_enable_16bit_bus(cy_true);
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#else
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   /* Astoria and GPMC are already in 8 bit mode, jsut initialize PNAND_CFG */
 
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   /* Astoria and GPMC are already in 8 bit mode, just initialize PNAND_CFG */
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        ast_p_nand_casdi_write(CY_AS_MEM_PNAND_CFG, 0x0000);
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#endif
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