← Back to branch summary

~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

« back to all changes in this revision

Viewing changes to drivers/net/wireless/rt2x00/rt2800lib.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

Show diffs side-by-side

added added

removed removed

Lines of Context:
drivers/net/wireless/rt2x00/rt2800lib.c
400
400
        if (rt2800_wait_csr_ready(rt2x00dev))
401
401
                return -EBUSY;
402
402
 
403
 
        if (rt2x00_is_pci(rt2x00dev))
 
403
        if (rt2x00_is_pci(rt2x00dev)) {
 
404
                if (rt2x00_rt(rt2x00dev, RT5390)) {
 
405
                        rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 
406
                        rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 
407
                        rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 
408
                        rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 
409
                }
404
410
                rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 
411
        }
405
412
 
406
413
        /*
407
414
         * Disable DMA, will be reenabled later when enabling
465
472
                           test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466
473
        rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467
474
                           test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468
 
        rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469
 
        rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470
 
        rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 
475
        rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 
476
                           txdesc->u.ht.mpdu_density);
 
477
        rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 
478
        rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
471
479
        rt2x00_set_field32(&word, TXWI_W0_BW,
472
480
                           test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473
481
        rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474
482
                           test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475
 
        rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 
483
        rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
476
484
        rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477
485
        rt2x00_desc_write(txwi, 0, word);
478
486
 
481
489
                           test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482
490
        rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483
491
                           test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484
 
        rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 
492
        rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
485
493
        rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486
494
                           test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487
495
                           txdesc->key_idx : 0xff);
674
682
         * confuse the rate control algortihm by providing clearly wrong
675
683
         * data.
676
684
         */
677
 
        if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
 
685
        if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
678
686
                skbdesc->tx_rate_idx = real_mcs;
679
687
                mcs = real_mcs;
680
688
        }
681
689
 
 
690
        if (aggr == 1 || ampdu == 1)
 
691
                __set_bit(TXDONE_AMPDU, &txdesc.flags);
 
692
 
682
693
        /*
683
694
         * Ralink has a retry mechanism using a global fallback
684
695
         * table. We setup this fallback table to try the immediate
719
730
        struct data_queue *queue;
720
731
        struct queue_entry *entry;
721
732
        u32 reg;
722
 
        u8 pid;
723
 
        int i;
724
 
 
725
 
        /*
726
 
         * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727
 
         * at most X times and also stop processing once the TX_STA_FIFO_VALID
728
 
         * flag is not set anymore.
729
 
         *
730
 
         * The legacy drivers use X=TX_RING_SIZE but state in a comment
731
 
         * that the TX_STA_FIFO stack has a size of 16. We stick to our
732
 
         * tx ring size for now.
733
 
         */
734
 
        for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
735
 
                rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
736
 
                if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
737
 
                        break;
738
 
 
739
 
                /*
740
 
                 * Skip this entry when it contains an invalid
741
 
                 * queue identication number.
 
733
        u8 qid;
 
734
 
 
735
        while (kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
 
736
 
 
737
                /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus
 
738
                 * qid is guaranteed to be one of the TX QIDs
742
739
                 */
743
 
                pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
744
 
                if (pid >= QID_RX)
745
 
                        continue;
746
 
 
747
 
                queue = rt2x00queue_get_queue(rt2x00dev, pid);
748
 
                if (unlikely(!queue))
749
 
                        continue;
 
740
                qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
 
741
                queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 
742
                if (unlikely(!queue)) {
 
743
                        WARNING(rt2x00dev, "Got TX status for an unavailable "
 
744
                                           "queue %u, dropping\n", qid);
 
745
                        continue;
 
746
                }
750
747
 
751
748
                /*
752
749
                 * Inside each queue, we process each entry in a chronological
773
770
        struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774
771
        unsigned int beacon_base;
775
772
        unsigned int padding_len;
776
 
        u32 reg;
 
773
        u32 orig_reg, reg;
777
774
 
778
775
        /*
779
776
         * Disable beaconing while we are reloading the beacon data,
780
777
         * otherwise we might be sending out invalid data.
781
778
         */
782
779
        rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 
780
        orig_reg = reg;
783
781
        rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
784
782
        rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
785
783
 
810
808
         * Write entire beacon with TXWI and padding to register.
811
809
         */
812
810
        padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
813
 
        skb_pad(entry->skb, padding_len);
 
811
        if (padding_len && skb_pad(entry->skb, padding_len)) {
 
812
                ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 
813
                /* skb freed by skb_pad() on failure */
 
814
                entry->skb = NULL;
 
815
                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 
816
                return;
 
817
        }
 
818
 
814
819
        beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
815
820
        rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
816
821
                                   entry->skb->len + padding_len);
818
823
        /*
819
824
         * Enable beaconing again.
820
825
         */
821
 
        rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
822
 
        rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
823
826
        rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824
827
        rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825
828
 
831
834
}
832
835
EXPORT_SYMBOL_GPL(rt2800_write_beacon);
833
836
 
834
 
static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
835
 
                                       unsigned int beacon_base)
 
837
static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 
838
                                                unsigned int beacon_base)
836
839
{
837
840
        int i;
838
841
 
845
848
                rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846
849
}
847
850
 
 
851
void rt2800_clear_beacon(struct queue_entry *entry)
 
852
{
 
853
        struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 
854
        u32 reg;
 
855
 
 
856
        /*
 
857
         * Disable beaconing while we are reloading the beacon data,
 
858
         * otherwise we might be sending out invalid data.
 
859
         */
 
860
        rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 
861
        rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 
862
        rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 
863
 
 
864
        /*
 
865
         * Clear beacon.
 
866
         */
 
867
        rt2800_clear_beacon_register(rt2x00dev,
 
868
                                     HW_BEACON_OFFSET(entry->entry_idx));
 
869
 
 
870
        /*
 
871
         * Enabled beaconing again.
 
872
         */
 
873
        rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 
874
        rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 
875
}
 
876
EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 
877
 
848
878
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
849
879
const struct rt2x00debug rt2800_rt2x00debug = {
850
880
        .owner  = THIS_MODULE,
905
935
        unsigned int ledmode =
906
936
                rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
907
937
                                   EEPROM_FREQ_LED_MODE);
908
 
 
909
 
        if (led->type == LED_TYPE_RADIO) {
910
 
                rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
911
 
                                      enabled ? 0x20 : 0);
912
 
        } else if (led->type == LED_TYPE_ASSOC) {
913
 
                rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
914
 
                                      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
915
 
        } else if (led->type == LED_TYPE_QUALITY) {
916
 
                /*
917
 
                 * The brightness is divided into 6 levels (0 - 5),
918
 
                 * The specs tell us the following levels:
919
 
                 *      0, 1 ,3, 7, 15, 31
920
 
                 * to determine the level in a simple way we can simply
921
 
                 * work with bitshifting:
922
 
                 *      (1 << level) - 1
923
 
                 */
924
 
                rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
925
 
                                      (1 << brightness / (LED_FULL / 6)) - 1,
926
 
                                      polarity);
 
938
        u32 reg;
 
939
 
 
940
        /* Check for SoC (SOC devices don't support MCU requests) */
 
941
        if (rt2x00_is_soc(led->rt2x00dev)) {
 
942
                rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 
943
 
 
944
                /* Set LED Polarity */
 
945
                rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 
946
 
 
947
                /* Set LED Mode */
 
948
                if (led->type == LED_TYPE_RADIO) {
 
949
                        rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 
950
                                           enabled ? 3 : 0);
 
951
                } else if (led->type == LED_TYPE_ASSOC) {
 
952
                        rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 
953
                                           enabled ? 3 : 0);
 
954
                } else if (led->type == LED_TYPE_QUALITY) {
 
955
                        rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 
956
                                           enabled ? 3 : 0);
 
957
                }
 
958
 
 
959
                rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 
960
 
 
961
        } else {
 
962
                if (led->type == LED_TYPE_RADIO) {
 
963
                        rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 
964
                                              enabled ? 0x20 : 0);
 
965
                } else if (led->type == LED_TYPE_ASSOC) {
 
966
                        rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 
967
                                              enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 
968
                } else if (led->type == LED_TYPE_QUALITY) {
 
969
                        /*
 
970
                         * The brightness is divided into 6 levels (0 - 5),
 
971
                         * The specs tell us the following levels:
 
972
                         *      0, 1 ,3, 7, 15, 31
 
973
                         * to determine the level in a simple way we can simply
 
974
                         * work with bitshifting:
 
975
                         *      (1 << level) - 1
 
976
                         */
 
977
                        rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 
978
                                              (1 << brightness / (LED_FULL / 6)) - 1,
 
979
                                              polarity);
 
980
                }
927
981
        }
928
982
}
929
983
 
1005
1059
 
1006
1060
        memset(&wcid_entry, 0, sizeof(wcid_entry));
1007
1061
        if (crypto->cmd == SET_KEY)
1008
 
                memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 
1062
                memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1009
1063
        rt2800_register_multiwrite(rt2x00dev, offset,
1010
1064
                                      &wcid_entry, sizeof(wcid_entry));
1011
1065
}
1060
1114
}
1061
1115
EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1062
1116
 
 
1117
static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
 
1118
{
 
1119
        int idx;
 
1120
        u32 offset, reg;
 
1121
 
 
1122
        /*
 
1123
         * Search for the first free pairwise key entry and return the
 
1124
         * corresponding index.
 
1125
         *
 
1126
         * Make sure the WCID starts _after_ the last possible shared key
 
1127
         * entry (>32).
 
1128
         *
 
1129
         * Since parts of the pairwise key table might be shared with
 
1130
         * the beacon frame buffers 6 & 7 we should only write into the
 
1131
         * first 222 entries.
 
1132
         */
 
1133
        for (idx = 33; idx <= 222; idx++) {
 
1134
                offset = MAC_WCID_ATTR_ENTRY(idx);
 
1135
                rt2800_register_read(rt2x00dev, offset, &reg);
 
1136
                if (!reg)
 
1137
                        return idx;
 
1138
        }
 
1139
        return -1;
 
1140
}
 
1141
 
1063
1142
int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1064
1143
                               struct rt2x00lib_crypto *crypto,
1065
1144
                               struct ieee80211_key_conf *key)
1066
1145
{
1067
1146
        struct hw_key_entry key_entry;
1068
1147
        u32 offset;
 
1148
        int idx;
1069
1149
 
1070
1150
        if (crypto->cmd == SET_KEY) {
1071
 
                /*
1072
 
                 * 1 pairwise key is possible per AID, this means that the AID
1073
 
                 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1074
 
                 * last possible shared key entry.
1075
 
                 *
1076
 
                 * Since parts of the pairwise key table might be shared with
1077
 
                 * the beacon frame buffers 6 & 7 we should only write into the
1078
 
                 * first 222 entries.
1079
 
                 */
1080
 
                if (crypto->aid > (222 - 32))
 
1151
                idx = rt2800_find_pairwise_keyslot(rt2x00dev);
 
1152
                if (idx < 0)
1081
1153
                        return -ENOSPC;
1082
 
 
1083
 
                key->hw_key_idx = 32 + crypto->aid;
 
1154
                key->hw_key_idx = idx;
1084
1155
 
1085
1156
                memcpy(key_entry.key, crypto->key,
1086
1157
                       sizeof(key_entry.key));
1155
1226
 
1156
1227
        if (flags & CONFIG_UPDATE_TYPE) {
1157
1228
                /*
1158
 
                 * Clear current synchronisation setup.
1159
 
                 */
1160
 
                rt2800_clear_beacon(rt2x00dev,
1161
 
                                    HW_BEACON_OFFSET(intf->beacon->entry_idx));
1162
 
                /*
1163
1229
                 * Enable synchronisation.
1164
1230
                 */
1165
1231
                rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1166
 
                rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1167
1232
                rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1168
 
                rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1169
 
                                   (conf->sync == TSF_SYNC_ADHOC ||
1170
 
                                    conf->sync == TSF_SYNC_AP_NONE));
1171
1233
                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1172
1234
 
1173
 
                /*
1174
 
                 * Enable pre tbtt interrupt for beaconing modes
1175
 
                 */
1176
 
                rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1177
 
                rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1178
 
                                   (conf->sync == TSF_SYNC_AP_NONE));
1179
 
                rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1180
 
 
 
1235
                if (conf->sync == TSF_SYNC_AP_NONE) {
 
1236
                        /*
 
1237
                         * Tune beacon queue transmit parameters for AP mode
 
1238
                         */
 
1239
                        rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
 
1240
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
 
1241
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
 
1242
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
 
1243
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
 
1244
                        rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
 
1245
                } else {
 
1246
                        rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
 
1247
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
 
1248
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
 
1249
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
 
1250
                        rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
 
1251
                        rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
 
1252
                }
1181
1253
        }
1182
1254
 
1183
1255
        if (flags & CONFIG_UPDATE_MAC) {
1361
1433
}
1362
1434
EXPORT_SYMBOL_GPL(rt2800_config_erp);
1363
1435
 
 
1436
static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
 
1437
                                     enum antenna ant)
 
1438
{
 
1439
        u32 reg;
 
1440
        u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
 
1441
        u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
 
1442
 
 
1443
        if (rt2x00_is_pci(rt2x00dev)) {
 
1444
                rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 
1445
                rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
 
1446
                rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 
1447
        } else if (rt2x00_is_usb(rt2x00dev))
 
1448
                rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
 
1449
                                   eesk_pin, 0);
 
1450
 
 
1451
        rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 
1452
        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
 
1453
        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
 
1454
        rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
 
1455
}
 
1456
 
1364
1457
void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1365
1458
{
1366
1459
        u8 r1;
1367
1460
        u8 r3;
 
1461
        u16 eeprom;
1368
1462
 
1369
1463
        rt2800_bbp_read(rt2x00dev, 1, &r1);
1370
1464
        rt2800_bbp_read(rt2x00dev, 3, &r3);
1372
1466
        /*
1373
1467
         * Configure the TX antenna.
1374
1468
         */
1375
 
        switch ((int)ant->tx) {
 
1469
        switch (ant->tx_chain_num) {
1376
1470
        case 1:
1377
1471
                rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1378
1472
                break;
1387
1481
        /*
1388
1482
         * Configure the RX antenna.
1389
1483
         */
1390
 
        switch ((int)ant->rx) {
 
1484
        switch (ant->rx_chain_num) {
1391
1485
        case 1:
 
1486
                if (rt2x00_rt(rt2x00dev, RT3070) ||
 
1487
                    rt2x00_rt(rt2x00dev, RT3090) ||
 
1488
                    rt2x00_rt(rt2x00dev, RT3390)) {
 
1489
                        rt2x00_eeprom_read(rt2x00dev,
 
1490
                                           EEPROM_NIC_CONF1, &eeprom);
 
1491
                        if (rt2x00_get_field16(eeprom,
 
1492
                                                EEPROM_NIC_CONF1_ANT_DIVERSITY))
 
1493
                                rt2800_set_ant_diversity(rt2x00dev,
 
1494
                                                rt2x00dev->default_ant.rx);
 
1495
                }
1392
1496
                rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1393
1497
                break;
1394
1498
        case 2:
1434
1538
{
1435
1539
        rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1436
1540
 
1437
 
        if (rt2x00dev->default_ant.tx == 1)
 
1541
        if (rt2x00dev->default_ant.tx_chain_num == 1)
1438
1542
                rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1439
1543
 
1440
 
        if (rt2x00dev->default_ant.rx == 1) {
 
1544
        if (rt2x00dev->default_ant.rx_chain_num == 1) {
1441
1545
                rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1442
1546
                rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1443
 
        } else if (rt2x00dev->default_ant.rx == 2)
 
1547
        } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1444
1548
                rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1445
1549
 
1446
1550
        if (rf->channel > 14) {
1447
1551
                /*
1448
1552
                 * When TX power is below 0, we should increase it by 7 to
1449
 
                 * make it a positive value (Minumum value is -7).
 
1553
                 * make it a positive value (Minimum value is -7).
1450
1554
                 * However this means that values between 0 and 7 have
1451
1555
                 * double meaning, and we should set a 7DBm boost flag.
1452
1556
                 */
1526
1630
        rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1527
1631
}
1528
1632
 
 
1633
 
 
1634
#define RT5390_POWER_BOUND     0x27
 
1635
#define RT5390_FREQ_OFFSET_BOUND       0x5f
 
1636
 
 
1637
static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
 
1638
                                         struct ieee80211_conf *conf,
 
1639
                                         struct rf_channel *rf,
 
1640
                                         struct channel_info *info)
 
1641
{
 
1642
        u8 rfcsr;
 
1643
 
 
1644
        rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
 
1645
        rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
 
1646
        rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
 
1647
        rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
 
1648
        rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
 
1649
 
 
1650
        rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
 
1651
        if (info->default_power1 > RT5390_POWER_BOUND)
 
1652
                rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
 
1653
        else
 
1654
                rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
 
1655
        rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 
1656
 
 
1657
        rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
 
1658
        rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
 
1659
        rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
 
1660
        rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
 
1661
        rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
 
1662
        rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 
1663
 
 
1664
        rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
 
1665
        if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
 
1666
                rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
 
1667
                                  RT5390_FREQ_OFFSET_BOUND);
 
1668
        else
 
1669
                rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
 
1670
        rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
 
1671
 
 
1672
        if (rf->channel <= 14) {
 
1673
                int idx = rf->channel-1;
 
1674
 
 
1675
                if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
 
1676
                        if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
 
1677
                                /* r55/r59 value array of channel 1~14 */
 
1678
                                static const char r55_bt_rev[] = {0x83, 0x83,
 
1679
                                        0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
 
1680
                                        0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
 
1681
                                static const char r59_bt_rev[] = {0x0e, 0x0e,
 
1682
                                        0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
 
1683
                                        0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
 
1684
 
 
1685
                                rt2800_rfcsr_write(rt2x00dev, 55,
 
1686
                                                   r55_bt_rev[idx]);
 
1687
                                rt2800_rfcsr_write(rt2x00dev, 59,
 
1688
                                                   r59_bt_rev[idx]);
 
1689
                        } else {
 
1690
                                static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
 
1691
                                        0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
 
1692
                                        0x88, 0x88, 0x86, 0x85, 0x84};
 
1693
 
 
1694
                                rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
 
1695
                        }
 
1696
                } else {
 
1697
                        if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
 
1698
                                static const char r55_nonbt_rev[] = {0x23, 0x23,
 
1699
                                        0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
 
1700
                                        0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
 
1701
                                static const char r59_nonbt_rev[] = {0x07, 0x07,
 
1702
                                        0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 
1703
                                        0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
 
1704
 
 
1705
                                rt2800_rfcsr_write(rt2x00dev, 55,
 
1706
                                                   r55_nonbt_rev[idx]);
 
1707
                                rt2800_rfcsr_write(rt2x00dev, 59,
 
1708
                                                   r59_nonbt_rev[idx]);
 
1709
                        } else if (rt2x00_rt(rt2x00dev, RT5390)) {
 
1710
                                static const char r59_non_bt[] = {0x8f, 0x8f,
 
1711
                                        0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
 
1712
                                        0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
 
1713
 
 
1714
                                rt2800_rfcsr_write(rt2x00dev, 59,
 
1715
                                                   r59_non_bt[idx]);
 
1716
                        }
 
1717
                }
 
1718
        }
 
1719
 
 
1720
        rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
 
1721
        rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
 
1722
        rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
 
1723
        rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 
1724
 
 
1725
        rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
 
1726
        rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
 
1727
        rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
 
1728
}
 
1729
 
1529
1730
static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1530
1731
                                  struct ieee80211_conf *conf,
1531
1732
                                  struct rf_channel *rf,
1550
1751
            rt2x00_rf(rt2x00dev, RF3052) ||
1551
1752
            rt2x00_rf(rt2x00dev, RF3320))
1552
1753
                rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 
1754
        else if (rt2x00_rf(rt2x00dev, RF5370) ||
 
1755
                 rt2x00_rf(rt2x00dev, RF5390))
 
1756
                rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1553
1757
        else
1554
1758
                rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1555
1759
 
1562
1766
        rt2800_bbp_write(rt2x00dev, 86, 0);
1563
1767
 
1564
1768
        if (rf->channel <= 14) {
1565
 
                if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1566
 
                        rt2800_bbp_write(rt2x00dev, 82, 0x62);
1567
 
                        rt2800_bbp_write(rt2x00dev, 75, 0x46);
1568
 
                } else {
1569
 
                        rt2800_bbp_write(rt2x00dev, 82, 0x84);
1570
 
                        rt2800_bbp_write(rt2x00dev, 75, 0x50);
 
1769
                if (!rt2x00_rt(rt2x00dev, RT5390)) {
 
1770
                        if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
 
1771
                                     &rt2x00dev->cap_flags)) {
 
1772
                                rt2800_bbp_write(rt2x00dev, 82, 0x62);
 
1773
                                rt2800_bbp_write(rt2x00dev, 75, 0x46);
 
1774
                        } else {
 
1775
                                rt2800_bbp_write(rt2x00dev, 82, 0x84);
 
1776
                                rt2800_bbp_write(rt2x00dev, 75, 0x50);
 
1777
                        }
1571
1778
                }
1572
1779
        } else {
1573
1780
                rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1574
1781
 
1575
 
                if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 
1782
                if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1576
1783
                        rt2800_bbp_write(rt2x00dev, 75, 0x46);
1577
1784
                else
1578
1785
                        rt2800_bbp_write(rt2x00dev, 75, 0x50);
1587
1794
        tx_pin = 0;
1588
1795
 
1589
1796
        /* Turn on unused PA or LNA when not using 1T or 1R */
1590
 
        if (rt2x00dev->default_ant.tx != 1) {
 
1797
        if (rt2x00dev->default_ant.tx_chain_num == 2) {
1591
1798
                rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1592
1799
                rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1593
1800
        }
1594
1801
 
1595
1802
        /* Turn on unused PA or LNA when not using 1T or 1R */
1596
 
        if (rt2x00dev->default_ant.rx != 1) {
 
1803
        if (rt2x00dev->default_ant.rx_chain_num == 2) {
1597
1804
                rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1598
1805
                rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1599
1806
        }
1637
1844
        rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1638
1845
}
1639
1846
 
 
1847
static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
 
1848
{
 
1849
        u8 tssi_bounds[9];
 
1850
        u8 current_tssi;
 
1851
        u16 eeprom;
 
1852
        u8 step;
 
1853
        int i;
 
1854
 
 
1855
        /*
 
1856
         * Read TSSI boundaries for temperature compensation from
 
1857
         * the EEPROM.
 
1858
         *
 
1859
         * Array idx               0    1    2    3    4    5    6    7    8
 
1860
         * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
 
1861
         * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
 
1862
         */
 
1863
        if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 
1864
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
 
1865
                tssi_bounds[0] = rt2x00_get_field16(eeprom,
 
1866
                                        EEPROM_TSSI_BOUND_BG1_MINUS4);
 
1867
                tssi_bounds[1] = rt2x00_get_field16(eeprom,
 
1868
                                        EEPROM_TSSI_BOUND_BG1_MINUS3);
 
1869
 
 
1870
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
 
1871
                tssi_bounds[2] = rt2x00_get_field16(eeprom,
 
1872
                                        EEPROM_TSSI_BOUND_BG2_MINUS2);
 
1873
                tssi_bounds[3] = rt2x00_get_field16(eeprom,
 
1874
                                        EEPROM_TSSI_BOUND_BG2_MINUS1);
 
1875
 
 
1876
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
 
1877
                tssi_bounds[4] = rt2x00_get_field16(eeprom,
 
1878
                                        EEPROM_TSSI_BOUND_BG3_REF);
 
1879
                tssi_bounds[5] = rt2x00_get_field16(eeprom,
 
1880
                                        EEPROM_TSSI_BOUND_BG3_PLUS1);
 
1881
 
 
1882
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
 
1883
                tssi_bounds[6] = rt2x00_get_field16(eeprom,
 
1884
                                        EEPROM_TSSI_BOUND_BG4_PLUS2);
 
1885
                tssi_bounds[7] = rt2x00_get_field16(eeprom,
 
1886
                                        EEPROM_TSSI_BOUND_BG4_PLUS3);
 
1887
 
 
1888
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
 
1889
                tssi_bounds[8] = rt2x00_get_field16(eeprom,
 
1890
                                        EEPROM_TSSI_BOUND_BG5_PLUS4);
 
1891
 
 
1892
                step = rt2x00_get_field16(eeprom,
 
1893
                                          EEPROM_TSSI_BOUND_BG5_AGC_STEP);
 
1894
        } else {
 
1895
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
 
1896
                tssi_bounds[0] = rt2x00_get_field16(eeprom,
 
1897
                                        EEPROM_TSSI_BOUND_A1_MINUS4);
 
1898
                tssi_bounds[1] = rt2x00_get_field16(eeprom,
 
1899
                                        EEPROM_TSSI_BOUND_A1_MINUS3);
 
1900
 
 
1901
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
 
1902
                tssi_bounds[2] = rt2x00_get_field16(eeprom,
 
1903
                                        EEPROM_TSSI_BOUND_A2_MINUS2);
 
1904
                tssi_bounds[3] = rt2x00_get_field16(eeprom,
 
1905
                                        EEPROM_TSSI_BOUND_A2_MINUS1);
 
1906
 
 
1907
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
 
1908
                tssi_bounds[4] = rt2x00_get_field16(eeprom,
 
1909
                                        EEPROM_TSSI_BOUND_A3_REF);
 
1910
                tssi_bounds[5] = rt2x00_get_field16(eeprom,
 
1911
                                        EEPROM_TSSI_BOUND_A3_PLUS1);
 
1912
 
 
1913
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
 
1914
                tssi_bounds[6] = rt2x00_get_field16(eeprom,
 
1915
                                        EEPROM_TSSI_BOUND_A4_PLUS2);
 
1916
                tssi_bounds[7] = rt2x00_get_field16(eeprom,
 
1917
                                        EEPROM_TSSI_BOUND_A4_PLUS3);
 
1918
 
 
1919
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
 
1920
                tssi_bounds[8] = rt2x00_get_field16(eeprom,
 
1921
                                        EEPROM_TSSI_BOUND_A5_PLUS4);
 
1922
 
 
1923
                step = rt2x00_get_field16(eeprom,
 
1924
                                          EEPROM_TSSI_BOUND_A5_AGC_STEP);
 
1925
        }
 
1926
 
 
1927
        /*
 
1928
         * Check if temperature compensation is supported.
 
1929
         */
 
1930
        if (tssi_bounds[4] == 0xff)
 
1931
                return 0;
 
1932
 
 
1933
        /*
 
1934
         * Read current TSSI (BBP 49).
 
1935
         */
 
1936
        rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
 
1937
 
 
1938
        /*
 
1939
         * Compare TSSI value (BBP49) with the compensation boundaries
 
1940
         * from the EEPROM and increase or decrease tx power.
 
1941
         */
 
1942
        for (i = 0; i <= 3; i++) {
 
1943
                if (current_tssi > tssi_bounds[i])
 
1944
                        break;
 
1945
        }
 
1946
 
 
1947
        if (i == 4) {
 
1948
                for (i = 8; i >= 5; i--) {
 
1949
                        if (current_tssi < tssi_bounds[i])
 
1950
                                break;
 
1951
                }
 
1952
        }
 
1953
 
 
1954
        return (i - 4) * step;
 
1955
}
 
1956
 
 
1957
static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
 
1958
                                      enum ieee80211_band band)
 
1959
{
 
1960
        u16 eeprom;
 
1961
        u8 comp_en;
 
1962
        u8 comp_type;
 
1963
        int comp_value = 0;
 
1964
 
 
1965
        rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
 
1966
 
 
1967
        /*
 
1968
         * HT40 compensation not required.
 
1969
         */
 
1970
        if (eeprom == 0xffff ||
 
1971
            !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
 
1972
                return 0;
 
1973
 
 
1974
        if (band == IEEE80211_BAND_2GHZ) {
 
1975
                comp_en = rt2x00_get_field16(eeprom,
 
1976
                                 EEPROM_TXPOWER_DELTA_ENABLE_2G);
 
1977
                if (comp_en) {
 
1978
                        comp_type = rt2x00_get_field16(eeprom,
 
1979
                                           EEPROM_TXPOWER_DELTA_TYPE_2G);
 
1980
                        comp_value = rt2x00_get_field16(eeprom,
 
1981
                                            EEPROM_TXPOWER_DELTA_VALUE_2G);
 
1982
                        if (!comp_type)
 
1983
                                comp_value = -comp_value;
 
1984
                }
 
1985
        } else {
 
1986
                comp_en = rt2x00_get_field16(eeprom,
 
1987
                                 EEPROM_TXPOWER_DELTA_ENABLE_5G);
 
1988
                if (comp_en) {
 
1989
                        comp_type = rt2x00_get_field16(eeprom,
 
1990
                                           EEPROM_TXPOWER_DELTA_TYPE_5G);
 
1991
                        comp_value = rt2x00_get_field16(eeprom,
 
1992
                                            EEPROM_TXPOWER_DELTA_VALUE_5G);
 
1993
                        if (!comp_type)
 
1994
                                comp_value = -comp_value;
 
1995
                }
 
1996
        }
 
1997
 
 
1998
        return comp_value;
 
1999
}
 
2000
 
 
2001
static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
 
2002
                                   enum ieee80211_band band, int power_level,
 
2003
                                   u8 txpower, int delta)
 
2004
{
 
2005
        u32 reg;
 
2006
        u16 eeprom;
 
2007
        u8 criterion;
 
2008
        u8 eirp_txpower;
 
2009
        u8 eirp_txpower_criterion;
 
2010
        u8 reg_limit;
 
2011
 
 
2012
        if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
 
2013
                return txpower;
 
2014
 
 
2015
        if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
 
2016
                /*
 
2017
                 * Check if eirp txpower exceed txpower_limit.
 
2018
                 * We use OFDM 6M as criterion and its eirp txpower
 
2019
                 * is stored at EEPROM_EIRP_MAX_TX_POWER.
 
2020
                 * .11b data rate need add additional 4dbm
 
2021
                 * when calculating eirp txpower.
 
2022
                 */
 
2023
                rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 
2024
                criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
 
2025
 
 
2026
                rt2x00_eeprom_read(rt2x00dev,
 
2027
                                   EEPROM_EIRP_MAX_TX_POWER, &eeprom);
 
2028
 
 
2029
                if (band == IEEE80211_BAND_2GHZ)
 
2030
                        eirp_txpower_criterion = rt2x00_get_field16(eeprom,
 
2031
                                                 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
 
2032
                else
 
2033
                        eirp_txpower_criterion = rt2x00_get_field16(eeprom,
 
2034
                                                 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
 
2035
 
 
2036
                eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
 
2037
                               (is_rate_b ? 4 : 0) + delta;
 
2038
 
 
2039
                reg_limit = (eirp_txpower > power_level) ?
 
2040
                                        (eirp_txpower - power_level) : 0;
 
2041
        } else
 
2042
                reg_limit = 0;
 
2043
 
 
2044
        return txpower + delta - reg_limit;
 
2045
}
 
2046
 
1640
2047
static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1641
 
                                  const int max_txpower)
 
2048
                                  enum ieee80211_band band,
 
2049
                                  int power_level)
1642
2050
{
1643
2051
        u8 txpower;
1644
 
        u8 max_value = (u8)max_txpower;
1645
2052
        u16 eeprom;
1646
 
        int i;
 
2053
        int i, is_rate_b;
1647
2054
        u32 reg;
1648
2055
        u8 r1;
1649
2056
        u32 offset;
1650
 
 
1651
 
        /*
1652
 
         * set to normal tx power mode: +/- 0dBm
 
2057
        int delta;
 
2058
 
 
2059
        /*
 
2060
         * Calculate HT40 compensation delta
 
2061
         */
 
2062
        delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
 
2063
 
 
2064
        /*
 
2065
         * calculate temperature compensation delta
 
2066
         */
 
2067
        delta += rt2800_get_gain_calibration_delta(rt2x00dev);
 
2068
 
 
2069
        /*
 
2070
         * set to normal bbp tx power control mode: +/- 0dBm
1653
2071
         */
1654
2072
        rt2800_bbp_read(rt2x00dev, 1, &r1);
1655
 
        rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
 
2073
        rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
1656
2074
        rt2800_bbp_write(rt2x00dev, 1, r1);
1657
 
 
1658
 
        /*
1659
 
         * The eeprom contains the tx power values for each rate. These
1660
 
         * values map to 100% tx power. Each 16bit word contains four tx
1661
 
         * power values and the order is the same as used in the TX_PWR_CFG
1662
 
         * registers.
1663
 
         */
1664
2075
        offset = TX_PWR_CFG_0;
1665
2076
 
1666
2077
        for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1674
2085
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1675
2086
                                   &eeprom);
1676
2087
 
1677
 
                /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
 
2088
                is_rate_b = i ? 0 : 1;
 
2089
                /*
 
2090
                 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1678
2091
                 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1679
 
                 * TX_PWR_CFG_4: unknown */
 
2092
                 * TX_PWR_CFG_4: unknown
 
2093
                 */
1680
2094
                txpower = rt2x00_get_field16(eeprom,
1681
2095
                                             EEPROM_TXPOWER_BYRATE_RATE0);
1682
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1683
 
                                   min(txpower, max_value));
 
2096
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2097
                                             power_level, txpower, delta);
 
2098
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
1684
2099
 
1685
 
                /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
 
2100
                /*
 
2101
                 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1686
2102
                 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1687
 
                 * TX_PWR_CFG_4: unknown */
 
2103
                 * TX_PWR_CFG_4: unknown
 
2104
                 */
1688
2105
                txpower = rt2x00_get_field16(eeprom,
1689
2106
                                             EEPROM_TXPOWER_BYRATE_RATE1);
1690
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1691
 
                                   min(txpower, max_value));
 
2107
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2108
                                             power_level, txpower, delta);
 
2109
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
1692
2110
 
1693
 
                /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
 
2111
                /*
 
2112
                 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
1694
2113
                 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1695
 
                 * TX_PWR_CFG_4: unknown */
 
2114
                 * TX_PWR_CFG_4: unknown
 
2115
                 */
1696
2116
                txpower = rt2x00_get_field16(eeprom,
1697
2117
                                             EEPROM_TXPOWER_BYRATE_RATE2);
1698
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1699
 
                                   min(txpower, max_value));
 
2118
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2119
                                             power_level, txpower, delta);
 
2120
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
1700
2121
 
1701
 
                /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
 
2122
                /*
 
2123
                 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1702
2124
                 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1703
 
                 * TX_PWR_CFG_4: unknown */
 
2125
                 * TX_PWR_CFG_4: unknown
 
2126
                 */
1704
2127
                txpower = rt2x00_get_field16(eeprom,
1705
2128
                                             EEPROM_TXPOWER_BYRATE_RATE3);
1706
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1707
 
                                   min(txpower, max_value));
 
2129
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2130
                                             power_level, txpower, delta);
 
2131
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
1708
2132
 
1709
2133
                /* read the next four txpower values */
1710
2134
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1711
2135
                                   &eeprom);
1712
2136
 
1713
 
                /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
 
2137
                is_rate_b = 0;
 
2138
                /*
 
2139
                 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1714
2140
                 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1715
 
                 * TX_PWR_CFG_4: unknown */
 
2141
                 * TX_PWR_CFG_4: unknown
 
2142
                 */
1716
2143
                txpower = rt2x00_get_field16(eeprom,
1717
2144
                                             EEPROM_TXPOWER_BYRATE_RATE0);
1718
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1719
 
                                   min(txpower, max_value));
 
2145
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2146
                                             power_level, txpower, delta);
 
2147
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
1720
2148
 
1721
 
                /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
 
2149
                /*
 
2150
                 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1722
2151
                 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1723
 
                 * TX_PWR_CFG_4: unknown */
 
2152
                 * TX_PWR_CFG_4: unknown
 
2153
                 */
1724
2154
                txpower = rt2x00_get_field16(eeprom,
1725
2155
                                             EEPROM_TXPOWER_BYRATE_RATE1);
1726
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1727
 
                                   min(txpower, max_value));
 
2156
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2157
                                             power_level, txpower, delta);
 
2158
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
1728
2159
 
1729
 
                /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
 
2160
                /*
 
2161
                 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1730
2162
                 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1731
 
                 * TX_PWR_CFG_4: unknown */
 
2163
                 * TX_PWR_CFG_4: unknown
 
2164
                 */
1732
2165
                txpower = rt2x00_get_field16(eeprom,
1733
2166
                                             EEPROM_TXPOWER_BYRATE_RATE2);
1734
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1735
 
                                   min(txpower, max_value));
 
2167
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2168
                                             power_level, txpower, delta);
 
2169
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
1736
2170
 
1737
 
                /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
 
2171
                /*
 
2172
                 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1738
2173
                 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1739
 
                 * TX_PWR_CFG_4: unknown */
 
2174
                 * TX_PWR_CFG_4: unknown
 
2175
                 */
1740
2176
                txpower = rt2x00_get_field16(eeprom,
1741
2177
                                             EEPROM_TXPOWER_BYRATE_RATE3);
1742
 
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1743
 
                                   min(txpower, max_value));
 
2178
                txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
 
2179
                                             power_level, txpower, delta);
 
2180
                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
1744
2181
 
1745
2182
                rt2800_register_write(rt2x00dev, offset, reg);
1746
2183
 
1749
2186
        }
1750
2187
}
1751
2188
 
 
2189
void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
 
2190
{
 
2191
        rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
 
2192
                              rt2x00dev->tx_power);
 
2193
}
 
2194
EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
 
2195
 
1752
2196
static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1753
2197
                                      struct rt2x00lib_conf *libconf)
1754
2198
{
1799
2243
        /* Always recalculate LNA gain before changing configuration */
1800
2244
        rt2800_config_lna_gain(rt2x00dev, libconf);
1801
2245
 
1802
 
        if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 
2246
        if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
1803
2247
                rt2800_config_channel(rt2x00dev, libconf->conf,
1804
2248
                                      &libconf->rf, &libconf->channel);
 
2249
                rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
 
2250
                                      libconf->conf->power_level);
 
2251
        }
1805
2252
        if (flags & IEEE80211_CONF_CHANGE_POWER)
1806
 
                rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
 
2253
                rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
 
2254
                                      libconf->conf->power_level);
1807
2255
        if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1808
2256
                rt2800_config_retry_limit(rt2x00dev, libconf);
1809
2257
        if (flags & IEEE80211_CONF_CHANGE_PS)
1832
2280
                if (rt2x00_rt(rt2x00dev, RT3070) ||
1833
2281
                    rt2x00_rt(rt2x00dev, RT3071) ||
1834
2282
                    rt2x00_rt(rt2x00dev, RT3090) ||
1835
 
                    rt2x00_rt(rt2x00dev, RT3390))
 
2283
                    rt2x00_rt(rt2x00dev, RT3390) ||
 
2284
                    rt2x00_rt(rt2x00dev, RT5390))
1836
2285
                        return 0x1c + (2 * rt2x00dev->lna_gain);
1837
2286
                else
1838
2287
                        return 0x2e + rt2x00dev->lna_gain;
1963
2412
        } else if (rt2800_is_305x_soc(rt2x00dev)) {
1964
2413
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1965
2414
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1966
 
                rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
 
2415
                rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
 
2416
        } else if (rt2x00_rt(rt2x00dev, RT5390)) {
 
2417
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 
2418
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 
2419
                rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1967
2420
        } else {
1968
2421
                rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1969
2422
                rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2032
2485
        rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2033
2486
        rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2034
2487
        rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2035
 
        rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
 
2488
        rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2036
2489
        rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2037
2490
        rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2038
2491
        rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2045
2498
        rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2046
2499
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2047
2500
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2048
 
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
 
2501
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2049
2502
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2050
2503
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2051
2504
        rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2058
2511
        rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2059
2512
        rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2060
2513
        rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2061
 
        rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
 
2514
        rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2062
2515
        rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2063
2516
        rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2064
2517
        rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2071
2524
        rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2072
2525
        rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2073
2526
        rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2074
 
        rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
 
2527
        rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2075
2528
        rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2076
2529
        rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2077
2530
        rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2084
2537
        rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2085
2538
        rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2086
2539
        rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2087
 
        rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
 
2540
        rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2088
2541
        rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2089
2542
        rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2090
2543
        rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2097
2550
        rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2098
2551
        rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2099
2552
        rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2100
 
        rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
 
2553
        rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2101
2554
        rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2102
2555
        rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2103
2556
        rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2180
2633
                rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2181
2634
                                              wcid, sizeof(wcid));
2182
2635
 
2183
 
                rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
 
2636
                rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2184
2637
                rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2185
2638
        }
2186
2639
 
2187
2640
        /*
2188
2641
         * Clear all beacons
2189
2642
         */
2190
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2191
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2192
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2193
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2194
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2195
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2196
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2197
 
        rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
 
2643
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
 
2644
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
 
2645
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
 
2646
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
 
2647
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
 
2648
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
 
2649
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
 
2650
        rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2198
2651
 
2199
2652
        if (rt2x00_is_usb(rt2x00dev)) {
2200
2653
                rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2201
2654
                rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2202
2655
                rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
 
2656
        } else if (rt2x00_is_pcie(rt2x00dev)) {
 
2657
                rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
 
2658
                rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
 
2659
                rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2203
2660
        }
2204
2661
 
2205
2662
        rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2335
2792
                     rt2800_wait_bbp_ready(rt2x00dev)))
2336
2793
                return -EACCES;
2337
2794
 
2338
 
        if (rt2800_is_305x_soc(rt2x00dev))
 
2795
        if (rt2x00_rt(rt2x00dev, RT5390)) {
 
2796
                rt2800_bbp_read(rt2x00dev, 4, &value);
 
2797
                rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
 
2798
                rt2800_bbp_write(rt2x00dev, 4, value);
 
2799
        }
 
2800
 
 
2801
        if (rt2800_is_305x_soc(rt2x00dev) ||
 
2802
            rt2x00_rt(rt2x00dev, RT5390))
2339
2803
                rt2800_bbp_write(rt2x00dev, 31, 0x08);
2340
2804
 
2341
2805
        rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2342
2806
        rt2800_bbp_write(rt2x00dev, 66, 0x38);
2343
2807
 
 
2808
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2809
                rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 
2810
 
2344
2811
        if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2345
2812
                rt2800_bbp_write(rt2x00dev, 69, 0x16);
2346
2813
                rt2800_bbp_write(rt2x00dev, 73, 0x12);
 
2814
        } else if (rt2x00_rt(rt2x00dev, RT5390)) {
 
2815
                rt2800_bbp_write(rt2x00dev, 69, 0x12);
 
2816
                rt2800_bbp_write(rt2x00dev, 73, 0x13);
 
2817
                rt2800_bbp_write(rt2x00dev, 75, 0x46);
 
2818
                rt2800_bbp_write(rt2x00dev, 76, 0x28);
 
2819
                rt2800_bbp_write(rt2x00dev, 77, 0x59);
2347
2820
        } else {
2348
2821
                rt2800_bbp_write(rt2x00dev, 69, 0x12);
2349
2822
                rt2800_bbp_write(rt2x00dev, 73, 0x10);
2354
2827
        if (rt2x00_rt(rt2x00dev, RT3070) ||
2355
2828
            rt2x00_rt(rt2x00dev, RT3071) ||
2356
2829
            rt2x00_rt(rt2x00dev, RT3090) ||
2357
 
            rt2x00_rt(rt2x00dev, RT3390)) {
 
2830
            rt2x00_rt(rt2x00dev, RT3390) ||
 
2831
            rt2x00_rt(rt2x00dev, RT5390)) {
2358
2832
                rt2800_bbp_write(rt2x00dev, 79, 0x13);
2359
2833
                rt2800_bbp_write(rt2x00dev, 80, 0x05);
2360
2834
                rt2800_bbp_write(rt2x00dev, 81, 0x33);
2366
2840
        }
2367
2841
 
2368
2842
        rt2800_bbp_write(rt2x00dev, 82, 0x62);
2369
 
        rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 
2843
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2844
                rt2800_bbp_write(rt2x00dev, 83, 0x7a);
 
2845
        else
 
2846
                rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2370
2847
 
2371
2848
        if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2372
2849
                rt2800_bbp_write(rt2x00dev, 84, 0x19);
 
2850
        else if (rt2x00_rt(rt2x00dev, RT5390))
 
2851
                rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2373
2852
        else
2374
2853
                rt2800_bbp_write(rt2x00dev, 84, 0x99);
2375
2854
 
2376
 
        rt2800_bbp_write(rt2x00dev, 86, 0x00);
 
2855
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2856
                rt2800_bbp_write(rt2x00dev, 86, 0x38);
 
2857
        else
 
2858
                rt2800_bbp_write(rt2x00dev, 86, 0x00);
 
2859
 
2377
2860
        rt2800_bbp_write(rt2x00dev, 91, 0x04);
2378
 
        rt2800_bbp_write(rt2x00dev, 92, 0x00);
 
2861
 
 
2862
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2863
                rt2800_bbp_write(rt2x00dev, 92, 0x02);
 
2864
        else
 
2865
                rt2800_bbp_write(rt2x00dev, 92, 0x00);
2379
2866
 
2380
2867
        if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2381
2868
            rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2382
2869
            rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2383
2870
            rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
 
2871
            rt2x00_rt(rt2x00dev, RT5390) ||
2384
2872
            rt2800_is_305x_soc(rt2x00dev))
2385
2873
                rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2386
2874
        else
2387
2875
                rt2800_bbp_write(rt2x00dev, 103, 0x00);
2388
2876
 
 
2877
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2878
                rt2800_bbp_write(rt2x00dev, 104, 0x92);
 
2879
 
2389
2880
        if (rt2800_is_305x_soc(rt2x00dev))
2390
2881
                rt2800_bbp_write(rt2x00dev, 105, 0x01);
 
2882
        else if (rt2x00_rt(rt2x00dev, RT5390))
 
2883
                rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2391
2884
        else
2392
2885
                rt2800_bbp_write(rt2x00dev, 105, 0x05);
2393
 
        rt2800_bbp_write(rt2x00dev, 106, 0x35);
 
2886
 
 
2887
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2888
                rt2800_bbp_write(rt2x00dev, 106, 0x03);
 
2889
        else
 
2890
                rt2800_bbp_write(rt2x00dev, 106, 0x35);
 
2891
 
 
2892
        if (rt2x00_rt(rt2x00dev, RT5390))
 
2893
                rt2800_bbp_write(rt2x00dev, 128, 0x12);
2394
2894
 
2395
2895
        if (rt2x00_rt(rt2x00dev, RT3071) ||
2396
2896
            rt2x00_rt(rt2x00dev, RT3090) ||
2397
 
            rt2x00_rt(rt2x00dev, RT3390)) {
 
2897
            rt2x00_rt(rt2x00dev, RT3390) ||
 
2898
            rt2x00_rt(rt2x00dev, RT5390)) {
2398
2899
                rt2800_bbp_read(rt2x00dev, 138, &value);
2399
2900
 
2400
2901
                rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2406
2907
                rt2800_bbp_write(rt2x00dev, 138, value);
2407
2908
        }
2408
2909
 
 
2910
        if (rt2x00_rt(rt2x00dev, RT5390)) {
 
2911
                int ant, div_mode;
 
2912
 
 
2913
                rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
 
2914
                div_mode = rt2x00_get_field16(eeprom,
 
2915
                                              EEPROM_NIC_CONF1_ANT_DIVERSITY);
 
2916
                ant = (div_mode == 3) ? 1 : 0;
 
2917
 
 
2918
                /* check if this is a Bluetooth combo card */
 
2919
                if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
 
2920
                        u32 reg;
 
2921
 
 
2922
                        rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 
2923
                        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
 
2924
                        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
 
2925
                        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
 
2926
                        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
 
2927
                        if (ant == 0)
 
2928
                                rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
 
2929
                        else if (ant == 1)
 
2930
                                rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
 
2931
                        rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
 
2932
                }
 
2933
 
 
2934
                rt2800_bbp_read(rt2x00dev, 152, &value);
 
2935
                if (ant == 0)
 
2936
                        rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
 
2937
                else
 
2938
                        rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
 
2939
                rt2800_bbp_write(rt2x00dev, 152, value);
 
2940
 
 
2941
                /* Init frequency calibration */
 
2942
                rt2800_bbp_write(rt2x00dev, 142, 1);
 
2943
                rt2800_bbp_write(rt2x00dev, 143, 57);
 
2944
        }
2409
2945
 
2410
2946
        for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2411
2947
                rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2436
2972
        rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2437
2973
        rt2800_bbp_write(rt2x00dev, 4, bbp);
2438
2974
 
 
2975
        rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
 
2976
        rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
 
2977
        rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
 
2978
 
2439
2979
        rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2440
2980
        rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2441
2981
        rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2491
3031
            !rt2x00_rt(rt2x00dev, RT3071) &&
2492
3032
            !rt2x00_rt(rt2x00dev, RT3090) &&
2493
3033
            !rt2x00_rt(rt2x00dev, RT3390) &&
 
3034
            !rt2x00_rt(rt2x00dev, RT5390) &&
2494
3035
            !rt2800_is_305x_soc(rt2x00dev))
2495
3036
                return 0;
2496
3037
 
2497
3038
        /*
2498
3039
         * Init RF calibration.
2499
3040
         */
2500
 
        rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2501
 
        rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2502
 
        rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2503
 
        msleep(1);
2504
 
        rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2505
 
        rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 
3041
        if (rt2x00_rt(rt2x00dev, RT5390)) {
 
3042
                rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
 
3043
                rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
 
3044
                rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 
3045
                msleep(1);
 
3046
                rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
 
3047
                rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
 
3048
        } else {
 
3049
                rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
 
3050
                rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
 
3051
                rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 
3052
                msleep(1);
 
3053
                rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
 
3054
                rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 
3055
        }
2506
3056
 
2507
3057
        if (rt2x00_rt(rt2x00dev, RT3070) ||
2508
3058
            rt2x00_rt(rt2x00dev, RT3071) ||
2510
3060
                rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2511
3061
                rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2512
3062
                rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2513
 
                rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
 
3063
                rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2514
3064
                rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2515
3065
                rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2516
3066
                rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2593
3143
                rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2594
3144
                rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2595
3145
                return 0;
 
3146
        } else if (rt2x00_rt(rt2x00dev, RT5390)) {
 
3147
                rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
 
3148
                rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
 
3149
                rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
 
3150
                rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
 
3151
                if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 
3152
                        rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
 
3153
                else
 
3154
                        rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
 
3155
                rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 
3156
                rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
 
3157
                rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
 
3158
                rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
 
3159
                rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
 
3160
                rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
 
3161
                rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 
3162
                rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
 
3163
                rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
 
3164
                rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
 
3165
 
 
3166
                rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 
3167
                rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 
3168
                rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
 
3169
                rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
 
3170
                rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 
3171
                if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 
3172
                        rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 
3173
                else
 
3174
                        rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
 
3175
                rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 
3176
                rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
 
3177
                rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
 
3178
                rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
 
3179
 
 
3180
                rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
 
3181
                rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 
3182
                rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 
3183
                rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 
3184
                rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
 
3185
                rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
 
3186
                rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
 
3187
                rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
 
3188
                rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
 
3189
                rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
 
3190
 
 
3191
                if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 
3192
                        rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
 
3193
                else
 
3194
                        rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
 
3195
                rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
 
3196
                rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
 
3197
                rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
 
3198
                rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
 
3199
                rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
 
3200
                if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 
3201
                        rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
 
3202
                else
 
3203
                        rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
 
3204
                rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
 
3205
                rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
 
3206
                rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
 
3207
 
 
3208
                rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
 
3209
                if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 
3210
                        rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
 
3211
                else
 
3212
                        rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
 
3213
                rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
 
3214
                rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
 
3215
                rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
 
3216
                rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
 
3217
                rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
 
3218
                rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
 
3219
 
 
3220
                rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
 
3221
                if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
 
3222
                        rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
 
3223
                else
 
3224
                        rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
 
3225
                rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 
3226
                rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2596
3227
        }
2597
3228
 
2598
3229
        if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2602
3233
                rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2603
3234
        } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2604
3235
                   rt2x00_rt(rt2x00dev, RT3090)) {
 
3236
                rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
 
3237
 
2605
3238
                rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2606
3239
                rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2607
3240
                rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2608
3241
 
2609
 
                rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2610
 
 
2611
3242
                rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2612
3243
                rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2613
3244
                if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2619
3250
                                rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2620
3251
                }
2621
3252
                rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
 
3253
 
 
3254
                rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
 
3255
                rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
 
3256
                rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2622
3257
        } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2623
3258
                rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2624
3259
                rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2642
3277
                        rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2643
3278
        }
2644
3279
 
2645
 
        /*
2646
 
         * Set back to initial state
2647
 
         */
2648
 
        rt2800_bbp_write(rt2x00dev, 24, 0);
2649
 
 
2650
 
        rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2651
 
        rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2652
 
        rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2653
 
 
2654
 
        /*
2655
 
         * set BBP back to BW20
2656
 
         */
2657
 
        rt2800_bbp_read(rt2x00dev, 4, &bbp);
2658
 
        rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2659
 
        rt2800_bbp_write(rt2x00dev, 4, bbp);
 
3280
        if (!rt2x00_rt(rt2x00dev, RT5390)) {
 
3281
                /*
 
3282
                 * Set back to initial state
 
3283
                 */
 
3284
                rt2800_bbp_write(rt2x00dev, 24, 0);
 
3285
 
 
3286
                rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
 
3287
                rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
 
3288
                rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 
3289
 
 
3290
                /*
 
3291
                 * Set BBP back to BW20
 
3292
                 */
 
3293
                rt2800_bbp_read(rt2x00dev, 4, &bbp);
 
3294
                rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
 
3295
                rt2800_bbp_write(rt2x00dev, 4, bbp);
 
3296
        }
2660
3297
 
2661
3298
        if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2662
3299
            rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2668
3305
        rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2669
3306
        rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2670
3307
 
2671
 
        rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2672
 
        rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2673
 
        if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2674
 
            rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2675
 
            rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2676
 
                if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2677
 
                        rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
 
3308
        if (!rt2x00_rt(rt2x00dev, RT5390)) {
 
3309
                rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
 
3310
                rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
 
3311
                if (rt2x00_rt(rt2x00dev, RT3070) ||
 
3312
                    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
 
3313
                    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
 
3314
                    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
 
3315
                        if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
 
3316
                                      &rt2x00dev->cap_flags))
 
3317
                                rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
 
3318
                }
 
3319
                rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
 
3320
                if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
 
3321
                        rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
 
3322
                                        rt2x00_get_field16(eeprom,
 
3323
                                                EEPROM_TXMIXER_GAIN_BG_VAL));
 
3324
                rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2678
3325
        }
2679
 
        rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2680
 
        if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2681
 
                rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2682
 
                                  rt2x00_get_field16(eeprom,
2683
 
                                                   EEPROM_TXMIXER_GAIN_BG_VAL));
2684
 
        rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2685
3326
 
2686
3327
        if (rt2x00_rt(rt2x00dev, RT3090)) {
2687
3328
                rt2800_bbp_read(rt2x00dev, 138, &bbp);
2688
3329
 
 
3330
                /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
2689
3331
                rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2690
3332
                if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2691
3333
                        rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2719
3361
                rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2720
3362
        }
2721
3363
 
2722
 
        if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
 
3364
        if (rt2x00_rt(rt2x00dev, RT3070)) {
2723
3365
                rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2724
 
                if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2725
 
                    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
 
3366
                if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
2726
3367
                        rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2727
3368
                else
2728
3369
                        rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2732
3373
                rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2733
3374
        }
2734
3375
 
 
3376
        if (rt2x00_rt(rt2x00dev, RT5390)) {
 
3377
                rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
 
3378
                rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
 
3379
                rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
 
3380
 
 
3381
                rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
 
3382
                rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
 
3383
                rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
 
3384
 
 
3385
                rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
 
3386
                rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
 
3387
                rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
 
3388
        }
 
3389
 
2735
3390
        return 0;
2736
3391
}
2737
3392
 
2980
3635
                                   default_lna_gain);
2981
3636
        rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2982
3637
 
2983
 
        rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2984
 
        if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2985
 
                rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2986
 
        if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2987
 
                rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2988
 
        rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2989
 
 
2990
3638
        return 0;
2991
3639
}
2992
3640
EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3003
3651
        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3004
3652
 
3005
3653
        /*
3006
 
         * Identify RF chipset.
 
3654
         * Identify RF chipset by EEPROM value
 
3655
         * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
 
3656
         * RT53xx: defined in "EEPROM_CHIP_ID" field
3007
3657
         */
3008
 
        value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3009
3658
        rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 
3659
        if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
 
3660
                rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
 
3661
        else
 
3662
                value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3010
3663
 
3011
3664
        rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3012
3665
                        value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3018
3671
            !rt2x00_rt(rt2x00dev, RT3071) &&
3019
3672
            !rt2x00_rt(rt2x00dev, RT3090) &&
3020
3673
            !rt2x00_rt(rt2x00dev, RT3390) &&
3021
 
            !rt2x00_rt(rt2x00dev, RT3572)) {
 
3674
            !rt2x00_rt(rt2x00dev, RT3572) &&
 
3675
            !rt2x00_rt(rt2x00dev, RT5390)) {
3022
3676
                ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3023
3677
                return -ENODEV;
3024
3678
        }
3032
3686
            !rt2x00_rf(rt2x00dev, RF3021) &&
3033
3687
            !rt2x00_rf(rt2x00dev, RF3022) &&
3034
3688
            !rt2x00_rf(rt2x00dev, RF3052) &&
3035
 
            !rt2x00_rf(rt2x00dev, RF3320)) {
 
3689
            !rt2x00_rf(rt2x00dev, RF3320) &&
 
3690
            !rt2x00_rf(rt2x00dev, RF5370) &&
 
3691
            !rt2x00_rf(rt2x00dev, RF5390)) {
3036
3692
                ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3037
3693
                return -ENODEV;
3038
3694
        }
3040
3696
        /*
3041
3697
         * Identify default antenna configuration.
3042
3698
         */
3043
 
        rt2x00dev->default_ant.tx =
 
3699
        rt2x00dev->default_ant.tx_chain_num =
3044
3700
            rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3045
 
        rt2x00dev->default_ant.rx =
 
3701
        rt2x00dev->default_ant.rx_chain_num =
3046
3702
            rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3047
3703
 
3048
 
        /*
3049
 
         * Read frequency offset and RF programming sequence.
3050
 
         */
3051
 
        rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3052
 
        rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3053
 
 
3054
 
        /*
3055
 
         * Read external LNA informations.
3056
 
         */
3057
3704
        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3058
3705
 
 
3706
        if (rt2x00_rt(rt2x00dev, RT3070) ||
 
3707
            rt2x00_rt(rt2x00dev, RT3090) ||
 
3708
            rt2x00_rt(rt2x00dev, RT3390)) {
 
3709
                value = rt2x00_get_field16(eeprom,
 
3710
                                EEPROM_NIC_CONF1_ANT_DIVERSITY);
 
3711
                switch (value) {
 
3712
                case 0:
 
3713
                case 1:
 
3714
                case 2:
 
3715
                        rt2x00dev->default_ant.tx = ANTENNA_A;
 
3716
                        rt2x00dev->default_ant.rx = ANTENNA_A;
 
3717
                        break;
 
3718
                case 3:
 
3719
                        rt2x00dev->default_ant.tx = ANTENNA_A;
 
3720
                        rt2x00dev->default_ant.rx = ANTENNA_B;
 
3721
                        break;
 
3722
                }
 
3723
        } else {
 
3724
                rt2x00dev->default_ant.tx = ANTENNA_A;
 
3725
                rt2x00dev->default_ant.rx = ANTENNA_A;
 
3726
        }
 
3727
 
 
3728
        /*
 
3729
         * Determine external LNA informations.
 
3730
         */
3059
3731
        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3060
 
                __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 
3732
                __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
3061
3733
        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3062
 
                __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 
3734
                __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
3063
3735
 
3064
3736
        /*
3065
3737
         * Detect if this device has an hardware controlled radio.
3066
3738
         */
3067
3739
        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3068
 
                __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
 
3740
                __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
 
3741
 
 
3742
        /*
 
3743
         * Detect if this device has Bluetooth co-existence.
 
3744
         */
 
3745
        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
 
3746
                __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
 
3747
 
 
3748
        /*
 
3749
         * Read frequency offset and RF programming sequence.
 
3750
         */
 
3751
        rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
 
3752
        rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3069
3753
 
3070
3754
        /*
3071
3755
         * Store led settings, for correct led behaviour.
3075
3759
        rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3076
3760
        rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3077
3761
 
3078
 
        rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
 
3762
        rt2x00dev->led_mcu_reg = eeprom;
3079
3763
#endif /* CONFIG_RT2X00_LIB_LEDS */
3080
3764
 
 
3765
        /*
 
3766
         * Check if support EIRP tx power limit feature.
 
3767
         */
 
3768
        rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
 
3769
 
 
3770
        if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
 
3771
                                        EIRP_MAX_TX_POWER_LIMIT)
 
3772
                __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
 
3773
 
3081
3774
        return 0;
3082
3775
}
3083
3776
EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3230
3923
        char *default_power1;
3231
3924
        char *default_power2;
3232
3925
        unsigned int i;
3233
 
        unsigned short max_power;
3234
3926
        u16 eeprom;
3235
3927
 
3236
3928
        /*
3297
3989
                   rt2x00_rf(rt2x00dev, RF2020) ||
3298
3990
                   rt2x00_rf(rt2x00dev, RF3021) ||
3299
3991
                   rt2x00_rf(rt2x00dev, RF3022) ||
3300
 
                   rt2x00_rf(rt2x00dev, RF3320)) {
 
3992
                   rt2x00_rf(rt2x00dev, RF3320) ||
 
3993
                   rt2x00_rf(rt2x00dev, RF5370) ||
 
3994
                   rt2x00_rf(rt2x00dev, RF5390)) {
3301
3995
                spec->num_channels = 14;
3302
3996
                spec->channels = rf_vals_3x;
3303
3997
        } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3355
4049
 
3356
4050
        spec->channels_info = info;
3357
4051
 
3358
 
        rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3359
 
        max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3360
4052
        default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3361
4053
        default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3362
4054
 
3363
4055
        for (i = 0; i < 14; i++) {
3364
 
                info[i].max_power = max_power;
3365
 
                info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3366
 
                info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
 
4056
                info[i].default_power1 = default_power1[i];
 
4057
                info[i].default_power2 = default_power2[i];
3367
4058
        }
3368
4059
 
3369
4060
        if (spec->num_channels > 14) {
3370
 
                max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3371
4061
                default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3372
4062
                default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3373
4063
 
3374
4064
                for (i = 14; i < spec->num_channels; i++) {
3375
 
                        info[i].max_power = max_power;
3376
 
                        info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3377
 
                        info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
 
4065
                        info[i].default_power1 = default_power1[i];
 
4066
                        info[i].default_power2 = default_power2[i];
3378
4067
                }
3379
4068
        }
3380
4069
 
3466
4155
        if (queue_idx >= 4)
3467
4156
                return 0;
3468
4157
 
3469
 
        queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 
4158
        queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
3470
4159
 
3471
4160
        /* Update WMM TXOP register */
3472
4161
        offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3524
4213
 
3525
4214
int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3526
4215
                        enum ieee80211_ampdu_mlme_action action,
3527
 
                        struct ieee80211_sta *sta, u16 tid, u16 *ssn)
 
4216
                        struct ieee80211_sta *sta, u16 tid, u16 *ssn,
 
4217
                        u8 buf_size)
3528
4218
{
3529
4219
        int ret = 0;
3530
4220