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#ifndef _BF518_IRQ_H_
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#define _BF518_IRQ_H_
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* Interrupt source definitions
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Event Source Core Event Name
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Events (highest priority) EMU 0
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Software Interrupt 1 IVG14 31
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Software Interrupt 2 --
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(lowest priority) IVG15 32 *
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#define NR_PERI_INTS (2 * 32)
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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#define IRQ_EMU 0 /* Emulation */
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#define IRQ_RST 1 /* reset */
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#define IRQ_NMI 2 /* Non Maskable */
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#define IRQ_EVX 3 /* Exception */
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#define IRQ_UNUSED 4 /* - unused interrupt */
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#define IRQ_HWERR 5 /* Hardware Error */
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#define IRQ_CORETMR 6 /* Core timer */
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#define BFIN_IRQ(x) ((x) + 7)
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#include <mach-common/irq.h>
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#define NR_PERI_INTS (2 * 32)
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#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
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#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
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#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
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#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
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#define IRQ_RTC BFIN_IRQ(14) /* RTC */
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#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
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#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
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#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
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#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
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#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
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#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
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#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
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#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
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#define IRQ_TWI BFIN_IRQ(20) /* TWI */
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#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
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#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
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#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
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#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
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#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
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#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
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#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
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#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
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#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
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#define IRQ_TWI BFIN_IRQ(20) /* TWI */
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#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
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#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
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#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
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#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
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#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
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#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
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#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
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#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
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#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
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#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
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#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
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#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
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#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
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#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
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#define SYS_IRQS BFIN_IRQ(63) /* 70 */
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#define GPIO_IRQ_BASE IRQ_PF0
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#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
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#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
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#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
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#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
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#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
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#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
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#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
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#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
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#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
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#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
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#define SYS_IRQS BFIN_IRQ(63) /* 70 */
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#define GPIO_IRQ_BASE IRQ_PF0
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#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
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#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
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#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
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#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
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#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
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#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
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#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
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#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
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#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
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/* IAR0 BIT FIELDS */
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA0_ERROR_POS 4
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#define IRQ_DMAR0_BLK_POS 8
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#define IRQ_DMAR1_BLK_POS 12
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#define IRQ_DMAR0_OVR_POS 16
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#define IRQ_DMAR1_OVR_POS 20
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#define IRQ_PPI_ERROR_POS 24
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#define IRQ_MAC_ERROR_POS 28
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#define IRQ_DMAR0_BLK_POS 8
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#define IRQ_DMAR1_BLK_POS 12
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#define IRQ_DMAR0_OVR_POS 16
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#define IRQ_DMAR1_OVR_POS 20
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#define IRQ_PPI_ERROR_POS 24
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#define IRQ_MAC_ERROR_POS 28
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/* IAR1 BIT FIELDS */
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#define IRQ_SPORT0_ERROR_POS 0
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#define IRQ_SPORT1_ERROR_POS 4
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#define IRQ_PTP_ERROR_POS 8
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#define IRQ_UART0_ERROR_POS 16
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#define IRQ_UART1_ERROR_POS 20
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#define IRQ_RTC_POS 24
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#define IRQ_PPI_POS 28
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#define IRQ_UART0_ERROR_POS 16
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#define IRQ_UART1_ERROR_POS 20
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#define IRQ_RTC_POS 24
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#define IRQ_PPI_POS 28
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/* IAR2 BIT FIELDS */
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#define IRQ_SPORT0_RX_POS 0
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#define IRQ_SPORT1_RX_POS 8
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#define IRQ_SPI1_POS 8
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#define IRQ_SPORT1_TX_POS 12
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#define IRQ_TWI_POS 16
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#define IRQ_SPI0_POS 20
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#define IRQ_UART0_RX_POS 24
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#define IRQ_UART0_TX_POS 28
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#define IRQ_TWI_POS 16
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#define IRQ_SPI0_POS 20
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#define IRQ_UART0_RX_POS 24
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#define IRQ_UART0_TX_POS 28
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/* IAR3 BIT FIELDS */
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#define IRQ_UART1_RX_POS 0
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#define IRQ_UART1_TX_POS 4
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#define IRQ_OPTSEC_POS 8
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#define IRQ_CNT_POS 12
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#define IRQ_MAC_RX_POS 16
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#define IRQ_UART1_RX_POS 0
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#define IRQ_UART1_TX_POS 4
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#define IRQ_OPTSEC_POS 8
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#define IRQ_CNT_POS 12
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#define IRQ_MAC_RX_POS 16
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#define IRQ_PORTH_INTA_POS 20
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#define IRQ_MAC_TX_POS 24
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#define IRQ_MAC_TX_POS 24
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#define IRQ_PORTH_INTB_POS 28
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/* IAR4 BIT FIELDS */
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/* IAR5 BIT FIELDS */
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#define IRQ_PORTG_INTA_POS 0
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#define IRQ_PORTG_INTB_POS 4
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#define IRQ_MEM_DMA0_POS 8
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#define IRQ_MEM_DMA1_POS 12
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#define IRQ_WATCH_POS 16
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#define IRQ_MEM_DMA0_POS 8
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#define IRQ_MEM_DMA1_POS 12
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#define IRQ_WATCH_POS 16
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#define IRQ_PORTF_INTA_POS 20
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#define IRQ_PORTF_INTB_POS 24
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#define IRQ_SPI0_ERROR_POS 28
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#define IRQ_SPI0_ERROR_POS 28
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/* IAR6 BIT FIELDS */
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#define IRQ_SPI1_ERROR_POS 0
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#define IRQ_RSI_INT0_POS 12
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#define IRQ_RSI_INT1_POS 16
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#define IRQ_PWM_TRIP_POS 20
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#define IRQ_PWM_SYNC_POS 24
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#define IRQ_PTP_STAT_POS 28
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#define IRQ_SPI1_ERROR_POS 0
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#define IRQ_RSI_INT0_POS 12
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#define IRQ_RSI_INT1_POS 16
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#define IRQ_PWM_TRIP_POS 20
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#define IRQ_PWM_SYNC_POS 24
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#define IRQ_PTP_STAT_POS 28
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#endif /* _BF518_IRQ_H_ */