1470
1470
* trace buffer at the maximum rate possible. The trace buffer is configured
1471
1471
* to store the PCs, wrapping when it is full. The performance counter is
1472
1472
* initialized to the max hardware count minus the number of events, N, between
1474
1474
* causing the generation of a HW counter interrupt which also stops the
1475
1475
* writing of the SPU PC values to the trace buffer. Hence the last PC
1476
1476
* written to the trace buffer is the SPU PC that we want. Unfortunately,