~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise : revision 29

arch/x86/include/asm/uv/uv_mmrs.h

* SGI UV MMR definitions

#ifndef _ASM_X86_UV_UV_MMRS_H

#define _ASM_X86_UV_UV_MMRS_H

* This file contains MMR definitions for both UV1 & UV2 hubs.

* In general, MMR addresses and structures are identical on both hubs.

* These MMRs are identified as:

* #define UVH_xxx <address>

* union uvh_xxx {

* unsigned long v;

* struct uvh_int_cmpd_s {

* } s;

* };

* If the MMR exists on both hub type but has different addresses or

* contents, the MMR definition is similar to:

* #define UV1H_xxx <uv1 address>

* #define UV2H_xxx <uv2address>

* #define UVH_xxx (is_uv1_hub() ? UV1H_xxx : UV2H_xxx)

* union uvh_xxx {

* unsigned long v;

* struct uv1h_int_cmpd_s { (Common fields only)

* } s;

* struct uv1h_int_cmpd_s { (Full UV1 definition)

* } s1;

* struct uv2h_int_cmpd_s { (Full UV2 definition)

* } s2;

* };

* Only essential difference are enumerated. For example, if the address is

* the same for both UV1 & UV2, only a single #define is generated. Likewise,

* if the contents is the same for both hubs, only the "s" structure is

* generated.

* If the MMR exists on ONLY 1 type of hub, no generic definition is

* generated:

* #define UVnH_xxx <uvn address>

* union uvnh_xxx {

* unsigned long v;

* struct uvh_int_cmpd_s {

* } sn;

* };

#define UV_MMR_ENABLE (1UL << 63)

#define UV1_HUB_PART_NUMBER 0x88a5

#define UV2_HUB_PART_NUMBER 0x8eb8

/* Compat: if this #define is present, UV headers support UV2 */

#define UV2_HUB_IS_SUPPORTED 1

/* KABI compat: if this #define is present, KABI hacks are present */

#define UV2_HUB_KABI_HACKS 1

/* ========================================================================= */

/* UVH_BAU_DATA_BROADCAST */

/* ========================================================================= */

#define UVH_BAU_DATA_BROADCAST 0x61688UL

#define UVH_BAU_DATA_BROADCAST_32 0x0440

#define UVH_BAU_DATA_BROADCAST_32 0x440

#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0

#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL

/* UVH_BAU_DATA_CONFIG */

/* ========================================================================= */

#define UVH_BAU_DATA_CONFIG 0x61680UL

#define UVH_BAU_DATA_CONFIG_32 0x0438

#define UVH_BAU_DATA_CONFIG_32 0x438

#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0

#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL

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/* UVH_EVENT_OCCURRED0 */

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/* ========================================================================= */

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#define UVH_EVENT_OCCURRED0 0x70000UL

#define UVH_EVENT_OCCURRED0_32 0x005e8

#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0

#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL

#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1

#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL

#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2

#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL

#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3

#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL

#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4

#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL

#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5

#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL

#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6

#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL

#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7

#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL

#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8

#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL

#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9

#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL

#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10

#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL

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#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11

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#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL

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#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12

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#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL

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#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13

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#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL

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#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14

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#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL

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#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15

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#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL

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#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16

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#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL

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#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17

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#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL

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#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18

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#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL

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#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19

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#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL

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#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20

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#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL

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#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21

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#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL

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#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22

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#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38

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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL

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#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39

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#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL

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#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40

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#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL

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#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41

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#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL

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#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42

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#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL

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#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43

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#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL

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#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44

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#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL

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#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45

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#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL

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#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46

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#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL

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#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47

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#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL

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#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48

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#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL

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#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49

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#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL

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#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50

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#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL

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#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51

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#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL

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#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52

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#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL

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#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53

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#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL

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#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54

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#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL

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#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55

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#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL

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#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56

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#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL

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#define UVH_EVENT_OCCURRED0_32 0x5e8

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#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0

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#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL

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#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1

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#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL

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#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2

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#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL

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#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3

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#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL

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#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4

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#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL

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#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5

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#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL

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#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6

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#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL

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#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7

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#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL

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#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8

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#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL

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#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9

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#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL

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#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10

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#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL

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#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11

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#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL

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#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12

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#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL

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#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13

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#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL

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#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14

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#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL

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#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15

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#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL

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#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16

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#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL

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#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17

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#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL

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#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18

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#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL

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#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19

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#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL

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#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20

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#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL

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#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21

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#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL

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#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22

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#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38

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#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL

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#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39

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#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL

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#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40

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#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL

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#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41

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#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL

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#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42

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#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL

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#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43

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#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL

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#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44

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#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL

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#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45

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#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49

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#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL

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#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50

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#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL

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#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51

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#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL

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#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52

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#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL

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#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53

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#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL

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#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54

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#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL

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#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55

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#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL

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#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56

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#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL

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#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0

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#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL

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#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1

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#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL

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#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2

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#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL

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#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3

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#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL

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#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4

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#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL

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#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5

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#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL

256

#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6

257

#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL

258

#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7

259

#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL

260

#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8

261

#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL

262

#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9

263

#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL

264

#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10

265

#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL

266

#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11

267

#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL

268

#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12

269

#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL

270

#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13

271

#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL

272

#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14

273

#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL

274

#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15

275

#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL

276

#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16

277

#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL

278

#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17

279

#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL

280

#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18

281

#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL

282

#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19

283

#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL

284

#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20

285

#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL

286

#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21

287

#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL

288

#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22

289

#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL

290

#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23

291

#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL

292

#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24

293

#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL

294

#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25

295

#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL

296

#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26

297

#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL

298

#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27

299

#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL

300

#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28

301

#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL

302

#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29

303

#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL

304

#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30

305

#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL

306

#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31

307

#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL

308

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32

309

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL

310

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33

311

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL

312

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34

313

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL

314

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35

315

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL

316

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36

317

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL

318

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37

319

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL

320

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38

321

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL

322

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39

323

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL

324

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40

325

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL

326

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41

327

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL

328

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42

329

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL

330

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43

331

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL

332

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44

333

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL

334

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45

335

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL

336

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46

337

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL

338

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47

339

#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL

340

#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48

341

#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL

342

#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49

343

#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL

344

#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50

345

#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL

346

#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51

347

#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL

348

#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52

349

#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL

350

#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53

351

#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL

352

#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54

353

#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL

354

#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55

355

#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL

356

#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56

357

#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL

358

#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57

359

#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL

360

#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58

361

#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL

362

192

363

union uvh_event_occurred0_u {

193

364

unsigned long v;

194

struct uvh_event_occurred0_s {

365

struct uv1h_event_occurred0_s {

195

366

unsigned long lb_hcerr : 1; /* RW, W1C */

196

367

unsigned long gr0_hcerr : 1; /* RW, W1C */

197

368

unsigned long gr1_hcerr : 1; /* RW, W1C */

250

421

unsigned long bau_data : 1; /* RW, W1C */

251

422

unsigned long power_management_req : 1; /* RW, W1C */

252

423

unsigned long rsvd_57_63 : 7; /* */

253

} s;

424

} s1;

425

struct uv2h_event_occurred0_s {

426

unsigned long lb_hcerr : 1; /* RW */

427

unsigned long qp_hcerr : 1; /* RW */

428

unsigned long rh_hcerr : 1; /* RW */

429

unsigned long lh0_hcerr : 1; /* RW */

430

unsigned long lh1_hcerr : 1; /* RW */

431

unsigned long gr0_hcerr : 1; /* RW */

432

unsigned long gr1_hcerr : 1; /* RW */

433

unsigned long ni0_hcerr : 1; /* RW */

434

unsigned long ni1_hcerr : 1; /* RW */

435

unsigned long lb_aoerr0 : 1; /* RW */

436

unsigned long qp_aoerr0 : 1; /* RW */

437

unsigned long rh_aoerr0 : 1; /* RW */

438

unsigned long lh0_aoerr0 : 1; /* RW */

439

unsigned long lh1_aoerr0 : 1; /* RW */

440

unsigned long gr0_aoerr0 : 1; /* RW */

441

unsigned long gr1_aoerr0 : 1; /* RW */

442

unsigned long xb_aoerr0 : 1; /* RW */

443

unsigned long rt_aoerr0 : 1; /* RW */

444

unsigned long ni0_aoerr0 : 1; /* RW */

445

unsigned long ni1_aoerr0 : 1; /* RW */

446

unsigned long lb_aoerr1 : 1; /* RW */

447

unsigned long qp_aoerr1 : 1; /* RW */

448

unsigned long rh_aoerr1 : 1; /* RW */

449

unsigned long lh0_aoerr1 : 1; /* RW */

450

unsigned long lh1_aoerr1 : 1; /* RW */

451

unsigned long gr0_aoerr1 : 1; /* RW */

452

unsigned long gr1_aoerr1 : 1; /* RW */

453

unsigned long xb_aoerr1 : 1; /* RW */

454

unsigned long rt_aoerr1 : 1; /* RW */

455

unsigned long ni0_aoerr1 : 1; /* RW */

456

unsigned long ni1_aoerr1 : 1; /* RW */

457

unsigned long system_shutdown_int : 1; /* RW */

458

unsigned long lb_irq_int_0 : 1; /* RW */

459

unsigned long lb_irq_int_1 : 1; /* RW */

460

unsigned long lb_irq_int_2 : 1; /* RW */

461

unsigned long lb_irq_int_3 : 1; /* RW */

462

unsigned long lb_irq_int_4 : 1; /* RW */

463

unsigned long lb_irq_int_5 : 1; /* RW */

464

unsigned long lb_irq_int_6 : 1; /* RW */

465

unsigned long lb_irq_int_7 : 1; /* RW */

466

unsigned long lb_irq_int_8 : 1; /* RW */

467

unsigned long lb_irq_int_9 : 1; /* RW */

468

unsigned long lb_irq_int_10 : 1; /* RW */

469

unsigned long lb_irq_int_11 : 1; /* RW */

470

unsigned long lb_irq_int_12 : 1; /* RW */

471

unsigned long lb_irq_int_13 : 1; /* RW */

472

unsigned long lb_irq_int_14 : 1; /* RW */

473

unsigned long lb_irq_int_15 : 1; /* RW */

474

unsigned long l1_nmi_int : 1; /* RW */

475

unsigned long stop_clock : 1; /* RW */

476

unsigned long asic_to_l1 : 1; /* RW */

477

unsigned long l1_to_asic : 1; /* RW */

478

unsigned long la_seq_trigger : 1; /* RW */

479

unsigned long ipi_int : 1; /* RW */

480

unsigned long extio_int0 : 1; /* RW */

481

unsigned long extio_int1 : 1; /* RW */

482

unsigned long extio_int2 : 1; /* RW */

483

unsigned long extio_int3 : 1; /* RW */

484

unsigned long profile_int : 1; /* RW */

485

unsigned long rsvd_59_63 : 5; /* */

486

} s2;

254

487

};

255

488

256

489

/* ========================================================================= */

257

490

/* UVH_EVENT_OCCURRED0_ALIAS */

258

491

/* ========================================================================= */

259

492

#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL

260

#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0

493

#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0

261

494

262

495

/* ========================================================================= */

263

496

/* UVH_GR0_TLB_INT0_CONFIG */

432

665

/* ========================================================================= */

433

666

#define UVH_INT_CMPC 0x22100UL

434

667

435

#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0

436

#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL

668

#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0

669

#define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT 0

670

#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT (is_uv1_hub() ? \

671

UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT : \

672

UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)

673

#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL

674

#define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL

675

#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK (is_uv1_hub() ? \

676

UV1H_INT_CMPC_REAL_TIME_CMPC_MASK : \

677

UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)

437

678

438

679

union uvh_int_cmpc_u {

439

680

unsigned long v;

448

689

/* ========================================================================= */

449

690

#define UVH_INT_CMPD 0x22180UL

450

691

451

#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0

452

#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL

692

#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0

693

#define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT 0

694

#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT (is_uv1_hub() ? \

695

UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT : \

696

UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)

697

#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL

698

#define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL

699

#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK (is_uv1_hub() ? \

700

UV1H_INT_CMPD_REAL_TIME_CMPD_MASK : \

701

UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)

453

702

454

703

union uvh_int_cmpd_u {

455

704

unsigned long v;

463

712

/* UVH_IPI_INT */

464

713

/* ========================================================================= */

465

714

#define UVH_IPI_INT 0x60500UL

466

#define UVH_IPI_INT_32 0x0348

715

#define UVH_IPI_INT_32 0x348

467

716

468

717

#define UVH_IPI_INT_VECTOR_SHFT 0

469

718

#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL

493

742

/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */

494

743

/* ========================================================================= */

495

744

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL

496

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0

745

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0

497

746

498

747

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4

499

748

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL

515

764

/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */

516

765

/* ========================================================================= */

517

766

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL

518

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8

767

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8

519

768

520

769

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4

521

770

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL

533

782

/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */

534

783

/* ========================================================================= */

535

784

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL

536

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0

785

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0

537

786

538

787

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4

539

788

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL

551

800

/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */

552

801

/* ========================================================================= */

553

802

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL

554

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68

803

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68

555

804

556

805

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0

557

806

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL

585

834

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL

586

835

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15

587

836

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL

837

588

838

union uvh_lb_bau_intd_software_acknowledge_u {

589

839

unsigned long v;

590

840

struct uvh_lb_bau_intd_software_acknowledge_s {

612

862

/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */

613

863

/* ========================================================================= */

614

864

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL

615

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70

865

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70

616

866

617

867

/* ========================================================================= */

618

868

/* UVH_LB_BAU_MISC_CONTROL */

619

869

/* ========================================================================= */

620

870

#define UVH_LB_BAU_MISC_CONTROL 0x320170UL

621

#define UVH_LB_BAU_MISC_CONTROL_32 0x00a10

871

#define UVH_LB_BAU_MISC_CONTROL_32 0xa10

622

872

623

873

#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0

624

874

#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL

628

878

#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL

629

879

#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10

630

880

#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL

631

#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11

632

#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL

881

#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11

882

#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL

633

883

#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14

634

884

#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL

635

885

#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15

650

900

#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL

651

901

#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28

652

902

#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL

653

#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48

654

#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL

903

904

#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0

905

#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL

906

#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8

907

#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL

908

#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9

909

#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL

910

#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10

911

#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL

912

#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11

913

#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL

914

#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14

915

#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL

916

#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15

917

#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL

918

#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16

919

#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL

920

#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20

921

#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL

922

#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21

923

#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL

924

#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22

925

#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL

926

#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23

927

#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL

928

#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24

929

#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL

930

#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27

931

#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL

932

#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28

933

#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL

934

#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48

935

#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL

936

937

#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0

938

#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL

939

#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8

940

#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL

941

#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9

942

#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL

943

#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10

944

#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL

945

#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11

946

#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL

947

#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14

948

#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL

949

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15

950

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL

951

#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16

952

#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL

953

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20

954

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL

955

#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21

956

#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL

957

#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22

958

#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL

959

#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23

960

#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL

961

#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24

962

#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL

963

#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27

964

#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL

965

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28

966

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL

967

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29

968

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL

969

#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30

970

#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL

971

#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31

972

#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL

973

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32

974

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL

975

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33

976

#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL

977

#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34

978

#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL

979

#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35

980

#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL

981

#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48

982

#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL

655

983

656

984

union uvh_lb_bau_misc_control_u {

657

985

unsigned long v;

660

988

unsigned long apic_mode : 1; /* RW */

661

989

unsigned long force_broadcast : 1; /* RW */

662

990

unsigned long force_lock_nop : 1; /* RW */

663

unsigned long csi_agent_presence_vector : 3; /* RW */

991

unsigned long qpi_agent_presence_vector : 3; /* RW */

992

unsigned long descriptor_fetch_mode : 1; /* RW */

993

unsigned long enable_intd_soft_ack_mode : 1; /* RW */

994

unsigned long intd_soft_ack_timeout_period : 4; /* RW */

995

unsigned long enable_dual_mapping_mode : 1; /* RW */

996

unsigned long vga_io_port_decode_enable : 1; /* RW */

997

unsigned long vga_io_port_16_bit_decode : 1; /* RW */

998

unsigned long suppress_dest_registration : 1; /* RW */

999

unsigned long programmed_initial_priority : 3; /* RW */

1000

unsigned long use_incoming_priority : 1; /* RW */

1001

unsigned long enable_programmed_initial_priority : 1; /* RW */

1002

unsigned long rsvd_29_63 : 35;

1003

} s;

1004

struct uv1h_lb_bau_misc_control_s {

1005

unsigned long rejection_delay : 8; /* RW */

1006

unsigned long apic_mode : 1; /* RW */

1007

unsigned long force_broadcast : 1; /* RW */

1008

unsigned long force_lock_nop : 1; /* RW */

1009

unsigned long qpi_agent_presence_vector : 3; /* RW */

664

1010

unsigned long descriptor_fetch_mode : 1; /* RW */

665

1011

unsigned long enable_intd_soft_ack_mode : 1; /* RW */

666

1012

unsigned long intd_soft_ack_timeout_period : 4; /* RW */

673

1019

unsigned long enable_programmed_initial_priority : 1; /* RW */

674

1020

unsigned long rsvd_29_47 : 19; /* */

675

1021

unsigned long fun : 16; /* RW */

676

} s;

1022

} s1;

1023

struct uv2h_lb_bau_misc_control_s {

1024

unsigned long rejection_delay : 8; /* RW */

1025

unsigned long apic_mode : 1; /* RW */

1026

unsigned long force_broadcast : 1; /* RW */

1027

unsigned long force_lock_nop : 1; /* RW */

1028

unsigned long qpi_agent_presence_vector : 3; /* RW */

1029

unsigned long descriptor_fetch_mode : 1; /* RW */

1030

unsigned long enable_intd_soft_ack_mode : 1; /* RW */

1031

unsigned long intd_soft_ack_timeout_period : 4; /* RW */

1032

unsigned long enable_dual_mapping_mode : 1; /* RW */

1033

unsigned long vga_io_port_decode_enable : 1; /* RW */

1034

unsigned long vga_io_port_16_bit_decode : 1; /* RW */

1035

unsigned long suppress_dest_registration : 1; /* RW */

1036

unsigned long programmed_initial_priority : 3; /* RW */

1037

unsigned long use_incoming_priority : 1; /* RW */

1038

unsigned long enable_programmed_initial_priority : 1; /* RW */

1039

unsigned long enable_automatic_apic_mode_selection : 1; /* RW */

1040

unsigned long apic_mode_status : 1; /* RO */

1041

unsigned long suppress_interrupts_to_self : 1; /* RW */

1042

unsigned long enable_lock_based_system_flush : 1; /* RW */

1043

unsigned long enable_extended_sb_status : 1; /* RW */

1044

unsigned long suppress_int_prio_udt_to_self : 1; /* RW */

1045

unsigned long use_legacy_descriptor_formats : 1; /* RW */

1046

unsigned long rsvd_36_47 : 12; /* */

1047

unsigned long fun : 16; /* RW */

1048

} s2;

677

1049

};

678

1050

679

1051

/* ========================================================================= */

680

1052

/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */

681

1053

/* ========================================================================= */

682

1054

#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL

683

#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8

1055

#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8

684

1056

685

1057

#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0

686

1058

#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL

703

1075

/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */

704

1076

/* ========================================================================= */

705

1077

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL

706

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0

1078

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0

707

1079

708

1080

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0

709

1081

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL

719

1091

/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */

720

1092

/* ========================================================================= */

721

1093

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL

722

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8

1094

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8

723

1095

724

1096

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0

725

1097

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL

735

1107

/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */

736

1108

/* ========================================================================= */

737

1109

#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL

738

#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0

1110

#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0

739

1111

740

1112

#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12

741

1113

#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL

754

1126

};

755

1127

756

1128

/* ========================================================================= */

757

/* UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK */

758

/* ========================================================================= */

759

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL

760

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0

761

762

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0

763

#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL

764

765

union uvh_lb_target_physical_apic_id_mask_u {

766

unsigned long v;

767

struct uvh_lb_target_physical_apic_id_mask_s {

768

unsigned long bit_enables : 32; /* RW */

769

unsigned long rsvd_32_63 : 32; /* */

770

} s;

771

};

772

773

/* ========================================================================= */

774

1129

/* UVH_NODE_ID */

775

1130

/* ========================================================================= */

776

1131

#define UVH_NODE_ID 0x0UL

785

1140

#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL

786

1141

#define UVH_NODE_ID_NODE_ID_SHFT 32

787

1142

#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL

788

#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48

789

#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL

790

#define UVH_NODE_ID_NI_PORT_SHFT 56

791

#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL

1143

1144

#define UV1H_NODE_ID_FORCE1_SHFT 0

1145

#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL

1146

#define UV1H_NODE_ID_MANUFACTURER_SHFT 1

1147

#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL

1148

#define UV1H_NODE_ID_PART_NUMBER_SHFT 12

1149

#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL

1150

#define UV1H_NODE_ID_REVISION_SHFT 28

1151

#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL

1152

#define UV1H_NODE_ID_NODE_ID_SHFT 32

1153

#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL

1154

#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48

1155

#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL

1156

#define UV1H_NODE_ID_NI_PORT_SHFT 56

1157

#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL

1158

1159

#define UV2H_NODE_ID_FORCE1_SHFT 0

1160

#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL

1161

#define UV2H_NODE_ID_MANUFACTURER_SHFT 1

1162

#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL

1163

#define UV2H_NODE_ID_PART_NUMBER_SHFT 12

1164

#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL

1165

#define UV2H_NODE_ID_REVISION_SHFT 28

1166

#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL

1167

#define UV2H_NODE_ID_NODE_ID_SHFT 32

1168

#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL

1169

#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50

1170

#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL

1171

#define UV2H_NODE_ID_NI_PORT_SHFT 57

1172

#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL

792

1173

793

1174

union uvh_node_id_u {

794

1175

unsigned long v;

798

1179

unsigned long part_number : 16; /* RO */

799

1180

unsigned long revision : 4; /* RO */

800

1181

unsigned long node_id : 15; /* RW */

1182

unsigned long rsvd_47_63 : 17;

1183

} s;

1184

struct uv1h_node_id_s {

1185

unsigned long force1 : 1; /* RO */

1186

unsigned long manufacturer : 11; /* RO */

1187

unsigned long part_number : 16; /* RO */

1188

unsigned long revision : 4; /* RO */

1189

unsigned long node_id : 15; /* RW */

801

1190

unsigned long rsvd_47 : 1; /* */

802

1191

unsigned long nodes_per_bit : 7; /* RW */

803

1192

unsigned long rsvd_55 : 1; /* */

804

1193

unsigned long ni_port : 4; /* RO */

805

1194

unsigned long rsvd_60_63 : 4; /* */

806

} s;

1195

} s1;

1196

struct uv2h_node_id_s {

1197

unsigned long force1 : 1; /* RO */

1198

unsigned long manufacturer : 11; /* RO */

1199

unsigned long part_number : 16; /* RO */

1200

unsigned long revision : 4; /* RO */

1201

unsigned long node_id : 15; /* RW */

1202

unsigned long rsvd_47_49 : 3; /* */

1203

unsigned long nodes_per_bit : 7; /* RO */

1204

unsigned long ni_port : 5; /* RO */

1205

unsigned long rsvd_62_63 : 2; /* */

1206

} s2;

807

1207

};

808

1208

809

1209

/* ========================================================================= */

954

1354

#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL

955

1355

#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6

956

1356

#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL

957

#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12

958

#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL

1357

1358

#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0

1359

#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL

1360

#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6

1361

#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL

1362

#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12

1363

#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL

1364

1365

#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0

1366

#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL

1367

#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6

1368

#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL

959

1369

960

1370

union uvh_rh_gam_config_mmr_u {

961

1371

unsigned long v;

962

1372

struct uvh_rh_gam_config_mmr_s {

963

1373

unsigned long m_skt : 6; /* RW */

964

1374

unsigned long n_skt : 4; /* RW */

1375

unsigned long rsvd_10_63 : 54;

1376

} s;

1377

struct uv1h_rh_gam_config_mmr_s {

1378

unsigned long m_skt : 6; /* RW */

1379

unsigned long n_skt : 4; /* RW */

965

1380

unsigned long rsvd_10_11: 2; /* */

966

1381

unsigned long mmiol_cfg : 1; /* RW */

967

1382

unsigned long rsvd_13_63: 51; /* */

968

} s;

1383

} s1;

1384

struct uv2h_rh_gam_config_mmr_s {

1385

unsigned long m_skt : 6; /* RW */

1386

unsigned long n_skt : 4; /* RW */

1387

unsigned long rsvd_10_63: 54; /* */

1388

} s2;

969

1389

};

970

1390

971

1391

/* ========================================================================= */

975

1395

976

1396

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28

977

1397

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL

978

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48

979

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL

980

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52

981

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL

982

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

983

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1398

1399

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28

1400

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL

1401

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48

1402

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL

1403

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52

1404

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL

1405

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1406

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1407

1408

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28

1409

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL

1410

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52

1411

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL

1412

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1413

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

984

1414

985

1415

union uvh_rh_gam_gru_overlay_config_mmr_u {

986

1416

unsigned long v;

987

1417

struct uvh_rh_gam_gru_overlay_config_mmr_s {

988

1418

unsigned long rsvd_0_27: 28; /* */

989

1419

unsigned long base : 18; /* RW */

1420

unsigned long rsvd_46_62 : 17;

1421

unsigned long enable : 1; /* RW */

1422

} s;

1423

struct uv1h_rh_gam_gru_overlay_config_mmr_s {

1424

unsigned long rsvd_0_27: 28; /* */

1425

unsigned long base : 18; /* RW */

990

1426

unsigned long rsvd_46_47: 2; /* */

991

1427

unsigned long gr4 : 1; /* RW */

992

1428

unsigned long rsvd_49_51: 3; /* */

993

1429

unsigned long n_gru : 4; /* RW */

994

1430

unsigned long rsvd_56_62: 7; /* */

995

1431

unsigned long enable : 1; /* RW */

996

} s;

1432

} s1;

1433

struct uv2h_rh_gam_gru_overlay_config_mmr_s {

1434

unsigned long rsvd_0_27: 28; /* */

1435

unsigned long base : 18; /* RW */

1436

unsigned long rsvd_46_51: 6; /* */

1437

unsigned long n_gru : 4; /* RW */

1438

unsigned long rsvd_56_62: 7; /* */

1439

unsigned long enable : 1; /* RW */

1440

} s2;

997

1441

};

998

1442

999

1443

/* ========================================================================= */

1001

1445

/* ========================================================================= */

1002

1446

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL

1003

1447

1004

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30

1005

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL

1006

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46

1007

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL

1008

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52

1009

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL

1010

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1011

#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1448

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30

1449

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL

1450

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46

1451

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL

1452

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52

1453

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL

1454

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1455

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1456

1457

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27

1458

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL

1459

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46

1460

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL

1461

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52

1462

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL

1463

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1464

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1012

1465

1013

1466

union uvh_rh_gam_mmioh_overlay_config_mmr_u {

1014

1467

unsigned long v;

1015

struct uvh_rh_gam_mmioh_overlay_config_mmr_s {

1468

struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {

1016

1469

unsigned long rsvd_0_29: 30; /* */

1017

1470

unsigned long base : 16; /* RW */

1018

1471

unsigned long m_io : 6; /* RW */

1019

1472

unsigned long n_io : 4; /* RW */

1020

1473

unsigned long rsvd_56_62: 7; /* */

1021

1474

unsigned long enable : 1; /* RW */

1022

} s;

1475

} s1;

1476

struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {

1477

unsigned long rsvd_0_26: 27; /* */

1478

unsigned long base : 19; /* RW */

1479

unsigned long m_io : 6; /* RW */

1480

unsigned long n_io : 4; /* RW */

1481

unsigned long rsvd_56_62: 7; /* */

1482

unsigned long enable : 1; /* RW */

1483

} s2;

1023

1484

};

1024

1485

1025

1486

/* ========================================================================= */

1029

1490

1030

1491

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26

1031

1492

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL

1032

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46

1033

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL

1034

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1035

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1493

1494

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26

1495

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL

1496

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46

1497

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL

1498

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1499

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1500

1501

#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26

1502

#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL

1503

#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63

1504

#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

1036

1505

1037

1506

union uvh_rh_gam_mmr_overlay_config_mmr_u {

1038

1507

unsigned long v;

1039

1508

struct uvh_rh_gam_mmr_overlay_config_mmr_s {

1040

1509

unsigned long rsvd_0_25: 26; /* */

1041

1510

unsigned long base : 20; /* RW */

1511

unsigned long rsvd_46_62 : 17;

1512

unsigned long enable : 1; /* RW */

1513

} s;

1514

struct uv1h_rh_gam_mmr_overlay_config_mmr_s {

1515

unsigned long rsvd_0_25: 26; /* */

1516

unsigned long base : 20; /* RW */

1042

1517

unsigned long dual_hub : 1; /* RW */

1043

1518

unsigned long rsvd_47_62: 16; /* */

1044

1519

unsigned long enable : 1; /* RW */

1045

} s;

1520

} s1;

1521

struct uv2h_rh_gam_mmr_overlay_config_mmr_s {

1522

unsigned long rsvd_0_25: 26; /* */

1523

unsigned long base : 20; /* RW */

1524

unsigned long rsvd_46_62: 17; /* */

1525

unsigned long enable : 1; /* RW */

1526

} s2;

1046

1527

};

1047

1528

1048

1529

/* ========================================================================= */

1099

1580

} s;

1100

1581

};

1101

1582

1583

/* ========================================================================= */

1584

/* UVH_SCRATCH5 */

1585

/* ========================================================================= */

1586

#define UVH_SCRATCH5 0x2d0200UL

1587

#define UVH_SCRATCH5_32 0x778

1588

1589

#define UVH_SCRATCH5_SCRATCH5_SHFT 0

1590

#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL

1591

1592

union uvh_scratch5_u {

1593

unsigned long v;

1594

struct uvh_scratch5_s {

1595

unsigned long scratch5 : 64; /* RW, W1CS */

1596

} s;

1597

};

1598

1599

/* ========================================================================= */

1600

/* UV2H_EVENT_OCCURRED2 */

1601

/* ========================================================================= */

1602

#define UV2H_EVENT_OCCURRED2 0x70100UL

1603

#define UV2H_EVENT_OCCURRED2_32 0xb68

1604

1605

#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0

1606

#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL

1607

#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1

1608

#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL

1609

#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2

1610

#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL

1611

#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3

1612

#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL

1613

#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4

1614

#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL

1615

#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5

1616

#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL

1617

#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6

1618

#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL

1619

#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7

1620

#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL

1621

#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8

1622

#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL

1623

#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9

1624

#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL

1625

#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10

1626

#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL

1627

#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11

1628

#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL

1629

#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12

1630

#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL

1631

#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13

1632

#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL

1633

#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14

1634

#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL

1635

#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15

1636

#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL

1637

#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16

1638

#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL

1639

#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17

1640

#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL

1641

#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18

1642

#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL

1643

#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19

1644

#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL

1645

#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20

1646

#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL

1647

#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21

1648

#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL

1649

#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22

1650

#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL

1651

#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23

1652

#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL

1653

#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24

1654

#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL

1655

#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25

1656

#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL

1657

#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26

1658

#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL

1659

#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27

1660

#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL

1661

#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28

1662

#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL

1663

#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29

1664

#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL

1665

#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30

1666

#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL

1667

#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31

1668

#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL

1669

1670

union uv2h_event_occurred2_u {

1671

unsigned long v;

1672

struct uv2h_event_occurred2_s {

1673

unsigned long rtc_0 : 1; /* RW */

1674

unsigned long rtc_1 : 1; /* RW */

1675

unsigned long rtc_2 : 1; /* RW */

1676

unsigned long rtc_3 : 1; /* RW */

1677

unsigned long rtc_4 : 1; /* RW */

1678

unsigned long rtc_5 : 1; /* RW */

1679

unsigned long rtc_6 : 1; /* RW */

1680

unsigned long rtc_7 : 1; /* RW */

1681

unsigned long rtc_8 : 1; /* RW */

1682

unsigned long rtc_9 : 1; /* RW */

1683

unsigned long rtc_10 : 1; /* RW */

1684

unsigned long rtc_11 : 1; /* RW */

1685

unsigned long rtc_12 : 1; /* RW */

1686

unsigned long rtc_13 : 1; /* RW */

1687

unsigned long rtc_14 : 1; /* RW */

1688

unsigned long rtc_15 : 1; /* RW */

1689

unsigned long rtc_16 : 1; /* RW */

1690

unsigned long rtc_17 : 1; /* RW */

1691

unsigned long rtc_18 : 1; /* RW */

1692

unsigned long rtc_19 : 1; /* RW */

1693

unsigned long rtc_20 : 1; /* RW */

1694

unsigned long rtc_21 : 1; /* RW */

1695

unsigned long rtc_22 : 1; /* RW */

1696

unsigned long rtc_23 : 1; /* RW */

1697

unsigned long rtc_24 : 1; /* RW */

1698

unsigned long rtc_25 : 1; /* RW */

1699

unsigned long rtc_26 : 1; /* RW */

1700

unsigned long rtc_27 : 1; /* RW */

1701

unsigned long rtc_28 : 1; /* RW */

1702

unsigned long rtc_29 : 1; /* RW */

1703

unsigned long rtc_30 : 1; /* RW */

1704

unsigned long rtc_31 : 1; /* RW */

1705

unsigned long rsvd_32_63: 32; /* */

1706

} s1;

1707

};

1708

1709

/* ========================================================================= */

1710

/* UV2H_EVENT_OCCURRED2_ALIAS */

1711

/* ========================================================================= */

1712

#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL

1713

#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70

1714

1715

/* ========================================================================= */

1716

/* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */

1717

/* ========================================================================= */

1718

#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL

1719

#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0

1720

1721

#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0

1722

#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL

1723

1724

union uv2h_lb_bau_sb_activation_status_2_u {

1725

unsigned long v;

1726

struct uv2h_lb_bau_sb_activation_status_2_s {

1727

unsigned long aux_error : 64; /* RW */

1728

} s1;

1729

};

1730

1731

/* ========================================================================= */

1732

/* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */

1733

/* ========================================================================= */

1734

#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL

1735

#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0

1736

1737

#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0

1738

#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL

1739

1740

union uv1h_lb_target_physical_apic_id_mask_u {

1741

unsigned long v;

1742

struct uv1h_lb_target_physical_apic_id_mask_s {

1743

unsigned long bit_enables : 32; /* RW */

1744

unsigned long rsvd_32_63 : 32; /* */

1745

} s1;

1746

};

1747

1102

1748

1103

1749

#endif /* __ASM_UV_MMRS_X86_H__ */

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