969
976
dev->state_saved = false;
979
struct pci_saved_state {
980
u32 config_space[16];
981
struct pci_cap_saved_data cap[0];
985
* pci_store_saved_state - Allocate and return an opaque struct containing
986
* the device saved state.
987
* @dev: PCI device that we're dealing with
989
* Rerturn NULL if no state or error.
991
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
993
struct pci_saved_state *state;
994
struct pci_cap_saved_state *tmp;
995
struct pci_cap_saved_data *cap;
996
struct hlist_node *pos;
999
if (!dev->state_saved)
1002
size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1004
hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1005
size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1007
state = kzalloc(size, GFP_KERNEL);
1011
memcpy(state->config_space, dev->saved_config_space,
1012
sizeof(state->config_space));
1015
hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1016
size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1017
memcpy(cap, &tmp->cap, len);
1018
cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1020
/* Empty cap_save terminates list */
1024
EXPORT_SYMBOL_GPL(pci_store_saved_state);
1027
* pci_load_saved_state - Reload the provided save state into struct pci_dev.
1028
* @dev: PCI device that we're dealing with
1029
* @state: Saved state returned from pci_store_saved_state()
1031
int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1033
struct pci_cap_saved_data *cap;
1035
dev->state_saved = false;
1040
memcpy(dev->saved_config_space, state->config_space,
1041
sizeof(state->config_space));
1045
struct pci_cap_saved_state *tmp;
1047
tmp = pci_find_saved_cap(dev, cap->cap_nr);
1048
if (!tmp || tmp->cap.size != cap->size)
1051
memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1052
cap = (struct pci_cap_saved_data *)((u8 *)cap +
1053
sizeof(struct pci_cap_saved_data) + cap->size);
1056
dev->state_saved = true;
1059
EXPORT_SYMBOL_GPL(pci_load_saved_state);
1062
* pci_load_and_free_saved_state - Reload the save state pointed to by state,
1063
* and free the memory allocated for it.
1064
* @dev: PCI device that we're dealing with
1065
* @state: Pointer to saved state returned from pci_store_saved_state()
1067
int pci_load_and_free_saved_state(struct pci_dev *dev,
1068
struct pci_saved_state **state)
1070
int ret = pci_load_saved_state(dev, *state);
1075
EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
972
1077
static int do_pci_enable_device(struct pci_dev *dev, int bars)
1828
1934
bridge->ari_enabled = 1;
1938
* pci_enable_ido - enable ID-based ordering on a device
1939
* @dev: the PCI device
1940
* @type: which types of IDO to enable
1942
* Enable ID-based ordering on @dev. @type can contain the bits
1943
* %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1944
* which types of transactions are allowed to be re-ordered.
1946
void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1951
pos = pci_pcie_cap(dev);
1955
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1956
if (type & PCI_EXP_IDO_REQUEST)
1957
ctrl |= PCI_EXP_IDO_REQ_EN;
1958
if (type & PCI_EXP_IDO_COMPLETION)
1959
ctrl |= PCI_EXP_IDO_CMP_EN;
1960
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1962
EXPORT_SYMBOL(pci_enable_ido);
1965
* pci_disable_ido - disable ID-based ordering on a device
1966
* @dev: the PCI device
1967
* @type: which types of IDO to disable
1969
void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1974
if (!pci_is_pcie(dev))
1977
pos = pci_pcie_cap(dev);
1981
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1982
if (type & PCI_EXP_IDO_REQUEST)
1983
ctrl &= ~PCI_EXP_IDO_REQ_EN;
1984
if (type & PCI_EXP_IDO_COMPLETION)
1985
ctrl &= ~PCI_EXP_IDO_CMP_EN;
1986
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1988
EXPORT_SYMBOL(pci_disable_ido);
1991
* pci_enable_obff - enable optimized buffer flush/fill
1993
* @type: type of signaling to use
1995
* Try to enable @type OBFF signaling on @dev. It will try using WAKE#
1996
* signaling if possible, falling back to message signaling only if
1997
* WAKE# isn't supported. @type should indicate whether the PCIe link
1998
* be brought out of L0s or L1 to send the message. It should be either
1999
* %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2001
* If your device can benefit from receiving all messages, even at the
2002
* power cost of bringing the link back up from a low power state, use
2003
* %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2007
* Zero on success, appropriate error number on failure.
2009
int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2016
if (!pci_is_pcie(dev))
2019
pos = pci_pcie_cap(dev);
2023
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2024
if (!(cap & PCI_EXP_OBFF_MASK))
2025
return -ENOTSUPP; /* no OBFF support at all */
2027
/* Make sure the topology supports OBFF as well */
2029
ret = pci_enable_obff(dev->bus->self, type);
2034
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2035
if (cap & PCI_EXP_OBFF_WAKE)
2036
ctrl |= PCI_EXP_OBFF_WAKE_EN;
2039
case PCI_EXP_OBFF_SIGNAL_L0:
2040
if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2041
ctrl |= PCI_EXP_OBFF_MSGA_EN;
2043
case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2044
ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2045
ctrl |= PCI_EXP_OBFF_MSGB_EN;
2048
WARN(1, "bad OBFF signal type\n");
2052
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2056
EXPORT_SYMBOL(pci_enable_obff);
2059
* pci_disable_obff - disable optimized buffer flush/fill
2062
* Disable OBFF on @dev.
2064
void pci_disable_obff(struct pci_dev *dev)
2069
if (!pci_is_pcie(dev))
2072
pos = pci_pcie_cap(dev);
2076
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2077
ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2078
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2080
EXPORT_SYMBOL(pci_disable_obff);
2083
* pci_ltr_supported - check whether a device supports LTR
2087
* True if @dev supports latency tolerance reporting, false otherwise.
2089
bool pci_ltr_supported(struct pci_dev *dev)
2094
if (!pci_is_pcie(dev))
2097
pos = pci_pcie_cap(dev);
2101
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2103
return cap & PCI_EXP_DEVCAP2_LTR;
2105
EXPORT_SYMBOL(pci_ltr_supported);
2108
* pci_enable_ltr - enable latency tolerance reporting
2111
* Enable LTR on @dev if possible, which means enabling it first on
2115
* Zero on success, errno on failure.
2117
int pci_enable_ltr(struct pci_dev *dev)
2123
if (!pci_ltr_supported(dev))
2126
pos = pci_pcie_cap(dev);
2130
/* Only primary function can enable/disable LTR */
2131
if (PCI_FUNC(dev->devfn) != 0)
2134
/* Enable upstream ports first */
2136
ret = pci_enable_ltr(dev->bus->self);
2141
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2142
ctrl |= PCI_EXP_LTR_EN;
2143
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2147
EXPORT_SYMBOL(pci_enable_ltr);
2150
* pci_disable_ltr - disable latency tolerance reporting
2153
void pci_disable_ltr(struct pci_dev *dev)
2158
if (!pci_ltr_supported(dev))
2161
pos = pci_pcie_cap(dev);
2165
/* Only primary function can enable/disable LTR */
2166
if (PCI_FUNC(dev->devfn) != 0)
2169
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2170
ctrl &= ~PCI_EXP_LTR_EN;
2171
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2173
EXPORT_SYMBOL(pci_disable_ltr);
2175
static int __pci_ltr_scale(int *val)
2179
while (*val > 1023) {
2180
*val = (*val + 31) / 32;
2187
* pci_set_ltr - set LTR latency values
2189
* @snoop_lat_ns: snoop latency in nanoseconds
2190
* @nosnoop_lat_ns: nosnoop latency in nanoseconds
2192
* Figure out the scale and set the LTR values accordingly.
2194
int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2196
int pos, ret, snoop_scale, nosnoop_scale;
2199
if (!pci_ltr_supported(dev))
2202
snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2203
nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2205
if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2206
nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2209
if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2210
(nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2213
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2217
val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2218
ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2222
val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2223
ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2229
EXPORT_SYMBOL(pci_set_ltr);
1831
2231
static int pci_acs_enable;
2869
3284
* @dev: the PCI device
2870
3285
* @decode: true = enable decoding, false = disable decoding
2871
3286
* @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2872
* @change_bridge: traverse ancestors and change bridges
3287
* @flags: traverse ancestors and change bridges
3288
* CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
2874
3290
int pci_set_vga_state(struct pci_dev *dev, bool decode,
2875
unsigned int command_bits, bool change_bridge)
3291
unsigned int command_bits, u32 flags)
2877
3293
struct pci_bus *bus;
2878
3294
struct pci_dev *bridge;
2882
WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
3298
WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
2884
3300
/* ARCH specific VGA enables */
2885
rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
3301
rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
2889
pci_read_config_word(dev, PCI_COMMAND, &cmd);
2891
cmd |= command_bits;
2893
cmd &= ~command_bits;
2894
pci_write_config_word(dev, PCI_COMMAND, cmd);
3305
if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3306
pci_read_config_word(dev, PCI_COMMAND, &cmd);
3308
cmd |= command_bits;
3310
cmd &= ~command_bits;
3311
pci_write_config_word(dev, PCI_COMMAND, cmd);
2896
if (change_bridge == false)
3314
if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
2899
3317
bus = dev->bus;