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Viewing changes to drivers/net/wireless/wl12xx/boot.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/net/wireless/wl12xx/boot.h
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#define PG_VER_MASK          0x3c
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#define PG_VER_OFFSET        2
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#define PG_MAJOR_VER_MASK    0x3
 
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#define PG_MAJOR_VER_OFFSET  0x0
 
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#define PG_MINOR_VER_MASK    0xc
 
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#define PG_MINOR_VER_OFFSET  0x2
 
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#define CMD_MBOX_ADDRESS     0x407B4
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#define POLARITY_LOW         BIT(1)
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#define FREF_CLK_POLARITY_BITS 0xfffff8ff
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#define CLK_REQ_OUTN_SEL       0x700
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/* PLL configuration algorithm for wl128x */
 
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#define SYS_CLK_CFG_REG              0x2200
 
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/* Bit[0]   -  0-TCXO,  1-FREF */
 
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#define MCS_PLL_CLK_SEL_FREF         BIT(0)
 
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/* Bit[3:2] - 01-TCXO, 10-FREF */
 
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#define WL_CLK_REQ_TYPE_FREF         BIT(3)
 
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#define WL_CLK_REQ_TYPE_PG2          (BIT(3) | BIT(2))
 
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/* Bit[4]   -  0-TCXO,  1-FREF */
 
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#define PRCM_CM_EN_MUX_WLAN_FREF     BIT(4)
 
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#define TCXO_ILOAD_INT_REG           0x2264
 
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#define TCXO_CLK_DETECT_REG          0x2266
 
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#define TCXO_DET_FAILED              BIT(4)
 
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#define FREF_ILOAD_INT_REG           0x2084
 
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#define FREF_CLK_DETECT_REG          0x2086
 
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#define FREF_CLK_DETECT_FAIL         BIT(4)
 
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/* Use this reg for masking during driver access */
 
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#define WL_SPARE_REG                 0x2320
 
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#define WL_SPARE_VAL                 BIT(2)
 
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/* Bit[6:5:3] -  mask wl write SYS_CLK_CFG[8:5:2:4] */
 
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#define WL_SPARE_MASK_8526           (BIT(6) | BIT(5) | BIT(3))
 
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#define PLL_LOCK_COUNTERS_REG        0xD8C
 
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#define PLL_LOCK_COUNTERS_COEX       0x0F
 
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#define PLL_LOCK_COUNTERS_MCS        0xF0
 
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#define MCS_PLL_OVERRIDE_REG         0xD90
 
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#define MCS_PLL_CONFIG_REG           0xD92
 
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#define MCS_SEL_IN_FREQ_MASK         0x0070
 
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#define MCS_SEL_IN_FREQ_SHIFT        4
 
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#define MCS_PLL_CONFIG_REG_VAL       0x73
 
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#define MCS_PLL_ENABLE_HP            (BIT(0) | BIT(1))
 
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#define MCS_PLL_M_REG                0xD94
 
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#define MCS_PLL_N_REG                0xD96
 
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#define MCS_PLL_M_REG_VAL            0xC8
 
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#define MCS_PLL_N_REG_VAL            0x07
 
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#define SDIO_IO_DS                   0xd14
 
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/* SDIO/wSPI DS configuration values */
 
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enum {
 
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        HCI_IO_DS_8MA = 0,
 
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        HCI_IO_DS_4MA = 1, /* default */
 
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        HCI_IO_DS_6MA = 2,
 
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        HCI_IO_DS_2MA = 3,
 
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};
 
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/* end PLL configuration algorithm for wl128x */
 
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#endif