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Viewing changes to arch/mips/sni/pcit.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
arch/mips/sni/pcit.c
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        .io_map_base    = SNI_PORT_BASE
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};
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static void enable_pcit_irq(unsigned int irq)
 
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static void enable_pcit_irq(struct irq_data *d)
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{
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        u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24);
 
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        u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
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        *(volatile u32 *)SNI_PCIT_INT_REG |= mask;
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}
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void disable_pcit_irq(unsigned int irq)
 
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void disable_pcit_irq(struct irq_data *d)
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{
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        u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24);
 
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        u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
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        *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
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}
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void end_pcit_irq(unsigned int irq)
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{
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        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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                enable_pcit_irq(irq);
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}
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static struct irq_chip pcit_irq_type = {
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        .name = "PCIT",
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        .ack = disable_pcit_irq,
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        .mask = disable_pcit_irq,
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        .mask_ack = disable_pcit_irq,
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        .unmask = enable_pcit_irq,
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        .end = end_pcit_irq,
 
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        .irq_mask = disable_pcit_irq,
 
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        .irq_unmask = enable_pcit_irq,
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};
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static void pcit_hwint1(void)
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        mips_cpu_irq_init();
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        for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
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                set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
 
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                irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
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        *(volatile u32 *)SNI_PCIT_INT_REG = 0;
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        sni_hwint = sni_pcit_hwint;
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        change_c0_status(ST0_IM, IE_IRQ1);
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        mips_cpu_irq_init();
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        for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
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                set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
 
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                irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
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        *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
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        sni_hwint = sni_pcit_hwint_cplus;
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        change_c0_status(ST0_IM, IE_IRQ0);