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Viewing changes to arch/blackfin/mach-bf537/ints-priority.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/blackfin/mach-bf537/ints-priority.c
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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#include <asm/irq_handler.h>
 
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#include <asm/bfin5xx_spi.h>
 
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#include <asm/bfin_sport.h>
 
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#include <asm/bfin_can.h>
 
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#include <asm/bfin_dma.h>
 
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#include <asm/dpmc.h>
 
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void __init program_IAR(void)
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{
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        /* Program the IAR0 Register with the configured priority */
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        SSYNC();
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}
 
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#define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE)  /* SPI_STAT */
 
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#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORT_STAT */
 
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#define PPI_ERR_MASK   (0xFFFF & ~FLD)  /* PPI_STATUS */
 
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#define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)  /* EMAC_SYSTAT */
 
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#define UART_ERR_MASK  (0x6)    /* UART_IIR */
 
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#define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)       /* CAN_GIF */
 
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static int error_int_mask;
 
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static void bf537_generic_error_mask_irq(struct irq_data *d)
 
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{
 
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        error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
 
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        if (!error_int_mask)
 
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                bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 
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}
 
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static void bf537_generic_error_unmask_irq(struct irq_data *d)
 
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{
 
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        bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 
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        error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
 
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}
 
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static struct irq_chip bf537_generic_error_irqchip = {
 
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        .name = "ERROR",
 
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        .irq_ack = bfin_ack_noop,
 
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        .irq_mask_ack = bf537_generic_error_mask_irq,
 
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        .irq_mask = bf537_generic_error_mask_irq,
 
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        .irq_unmask = bf537_generic_error_unmask_irq,
 
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};
 
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static void bf537_demux_error_irq(unsigned int int_err_irq,
 
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                                  struct irq_desc *inta_desc)
 
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{
 
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        int irq = 0;
 
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 
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        if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 
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                irq = IRQ_MAC_ERROR;
 
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        else
 
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#endif
 
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        if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 
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                irq = IRQ_SPORT0_ERROR;
 
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        else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 
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                irq = IRQ_SPORT1_ERROR;
 
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        else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 
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                irq = IRQ_PPI_ERROR;
 
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        else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 
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                irq = IRQ_CAN_ERROR;
 
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        else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 
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                irq = IRQ_SPI_ERROR;
 
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        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 
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                irq = IRQ_UART0_ERROR;
 
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        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
 
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                irq = IRQ_UART1_ERROR;
 
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        if (irq) {
 
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                if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
 
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                        bfin_handle_irq(irq);
 
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                else {
 
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                        switch (irq) {
 
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                        case IRQ_PPI_ERROR:
 
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                                bfin_write_PPI_STATUS(PPI_ERR_MASK);
 
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                                break;
 
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 
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                        case IRQ_MAC_ERROR:
 
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                                bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 
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                                break;
 
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#endif
 
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                        case IRQ_SPORT0_ERROR:
 
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                                bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 
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                                break;
 
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                        case IRQ_SPORT1_ERROR:
 
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                                bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 
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                                break;
 
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                        case IRQ_CAN_ERROR:
 
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                                bfin_write_CAN_GIS(CAN_ERR_MASK);
 
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                                break;
 
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                        case IRQ_SPI_ERROR:
 
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                                bfin_write_SPI_STAT(SPI_ERR_MASK);
 
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                                break;
 
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                        default:
 
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                                break;
 
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                        }
 
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                        pr_debug("IRQ %d:"
 
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                                 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 
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                                 irq);
 
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                }
 
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        } else
 
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                pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 
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                       __func__);
 
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}
 
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#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 
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static int mac_rx_int_mask;
 
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static void bf537_mac_rx_mask_irq(struct irq_data *d)
 
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{
 
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        mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
 
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        if (!mac_rx_int_mask)
 
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                bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
 
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}
 
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static void bf537_mac_rx_unmask_irq(struct irq_data *d)
 
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{
 
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        bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
 
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        mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
 
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}
 
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static struct irq_chip bf537_mac_rx_irqchip = {
 
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        .name = "ERROR",
 
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        .irq_ack = bfin_ack_noop,
 
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        .irq_mask_ack = bf537_mac_rx_mask_irq,
 
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        .irq_mask = bf537_mac_rx_mask_irq,
 
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        .irq_unmask = bf537_mac_rx_unmask_irq,
 
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};
 
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static void bf537_demux_mac_rx_irq(unsigned int int_irq,
 
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                                   struct irq_desc *desc)
 
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{
 
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        if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
 
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                bfin_handle_irq(IRQ_MAC_RX);
 
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        else
 
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                bfin_demux_gpio_irq(int_irq, desc);
 
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}
 
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#endif
 
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void __init init_mach_irq(void)
 
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{
 
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        int irq;
 
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#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
 
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        /* Clear EMAC Interrupt Status bits so we can demux it later */
 
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        bfin_write_EMAC_SYSTAT(-1);
 
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#endif
 
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        irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
 
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        for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
 
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                irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
 
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                                         handle_level_irq);
 
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#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 
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        irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
 
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        irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
 
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        irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
 
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        irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
 
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#endif
 
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}