~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);

1745

RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);

1746

dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);

1747

1748

rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);

1749

RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);

1750

RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);

1751

RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);

1752

1753

}

1754

1755

void dm_restore_dynamic_mechanism_state(struct net_device *dev)

1756

{

1757

struct r8192_priv *priv = ieee80211_priv(dev);

1758

u32 reg_ratr = priv->rate_adaptive.last_ratr;

1759

1760

if(!priv->up)

1761

{

1762

RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");

1763

return;

1764

}

1765

1766

1767

// Restore previous state for rate adaptive

1768

1769

if(priv->rate_adaptive.rate_adaptive_disabled)

1770

return;

1771

// TODO: Only 11n mode is implemented currently,

1772

if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||

1773

priv->ieee80211->mode==WIRELESS_MODE_N_5G))

1774

return;

1775

{

1776

/* 2007/11/15 MH Copy from 8190PCI. */

1777

u32 ratr_value;

1778

ratr_value = reg_ratr;

1779

if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled

1780

{

1781

ratr_value &=~ (RATE_ALL_OFDM_2SS);

1782

//DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);

1783

}

1784

//DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);

1785

//cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);

1786

write_nic_dword(dev, RATR0, ratr_value);

1787

write_nic_byte(dev, UFWP, 1);

1788

}

1789

//Resore TX Power Tracking Index

1790

if(priv->btxpower_trackingInit && priv->btxpower_tracking){

1791

dm_txpower_reset_recovery(dev);

1792

}

1793

1794

1795

//Restore BB Initial Gain

1796

1797

dm_bb_initialgain_restore(dev);

1798

1799

}

1800

1801

static void dm_bb_initialgain_restore(struct net_device *dev)

1802

{

1803

struct r8192_priv *priv = ieee80211_priv(dev);

1804

u32 bit_mask = 0x7f; //Bit0~ Bit6

1805

1806

if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)

1807

return;

1808

1809

//Disable Initial Gain

1810

//PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);

1811

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.

1812

rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);

1813

rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);

1814

rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);

1815

rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);

1816

bit_mask = bMaskByte2;

1817

rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);

1818

1819

RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);

1820

RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);

1821

RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);

1822

RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);

1823

RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);

1824

//Enable Initial Gain

1825

//PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);

1826

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.

1827

1828

}

1829

1830

1831

void dm_backup_dynamic_mechanism_state(struct net_device *dev)

1832

{

1833

struct r8192_priv *priv = ieee80211_priv(dev);

1834

1835

// Fsync to avoid reset

1836

priv->bswitch_fsync = false;

1837

priv->bfsync_processing = false;

1838

//Backup BB InitialGain

1839

dm_bb_initialgain_backup(dev);

1840

1841

}

1842

1843

1844

static void dm_bb_initialgain_backup(struct net_device *dev)

1845

{

1846

struct r8192_priv *priv = ieee80211_priv(dev);

1847

u32 bit_mask = bMaskByte0; //Bit0~ Bit6

1848

1849

if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)

1850

return;

1851

1852

//PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);

1853

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.

1854

priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);

1855

priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);

1856

priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);

1857

priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);

1858

bit_mask = bMaskByte2;

1859

priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);

1860

1861

RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);

1862

RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);

1863

RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);

1864

RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);

1865

RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);

1866

1867

}

1868

1869

#endif

1870

1871

void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)

1872

{

1873

if (dm_type == DIG_TYPE_THRESH_HIGH)

1874

{

1875

dm_digtable.rssi_high_thresh = dm_value;

1876

}

1877

else if (dm_type == DIG_TYPE_THRESH_LOW)

1878

{

1879

dm_digtable.rssi_low_thresh = dm_value;

1880

}

1881

else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)

1882

{

1883

dm_digtable.rssi_high_power_highthresh = dm_value;

1884

}

1885

else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)

1886

{

1887

dm_digtable.rssi_high_power_highthresh = dm_value;

1888

}

1889

else if (dm_type == DIG_TYPE_ENABLE)

1890

{

1891

dm_digtable.dig_state = DM_STA_DIG_MAX;

1892

dm_digtable.dig_enable_flag = true;

1893

}

1894

else if (dm_type == DIG_TYPE_DISABLE)

1895

{

1896

dm_digtable.dig_state = DM_STA_DIG_MAX;

1897

dm_digtable.dig_enable_flag = false;

1898

}

1899

else if (dm_type == DIG_TYPE_DBG_MODE)

1900

{

1901

if(dm_value >= DM_DBG_MAX)

1902

dm_value = DM_DBG_OFF;

1903

dm_digtable.dbg_mode = (u8)dm_value;

1904

}

1905

else if (dm_type == DIG_TYPE_RSSI)

1906

{

1907

if(dm_value > 100)

1908

dm_value = 30;

1909

dm_digtable.rssi_val = (long)dm_value;

1910

}

1911

else if (dm_type == DIG_TYPE_ALGORITHM)

1912

{

1913

if (dm_value >= DIG_ALGO_MAX)

1914

dm_value = DIG_ALGO_BY_FALSE_ALARM;

1915

if(dm_digtable.dig_algorithm != (u8)dm_value)

1916

dm_digtable.dig_algorithm_switch = 1;

1917

dm_digtable.dig_algorithm = (u8)dm_value;

1918

}

1919

else if (dm_type == DIG_TYPE_BACKOFF)

1920

{

1921

if(dm_value > 30)

1922

dm_value = 30;

1923

dm_digtable.backoff_val = (u8)dm_value;

1924

}

1925

else if(dm_type == DIG_TYPE_RX_GAIN_MIN)

1926

{

1927

if(dm_value == 0)

1928

dm_value = 0x1;

1929

dm_digtable.rx_gain_range_min = (u8)dm_value;

1930

}

1931

else if(dm_type == DIG_TYPE_RX_GAIN_MAX)

1932

{

1933

if(dm_value > 0x50)

1934

dm_value = 0x50;

1935

dm_digtable.rx_gain_range_max = (u8)dm_value;

1936

}

1937

}

1938

1103

dm_CCKTxPowerAdjust_ThermalMeter(priv, binch14);

1104

}

1939

1105

1940

1106

/* Set DIG scheme init value. */

1941

static void dm_dig_init(struct net_device *dev)

1107

static void dm_dig_init(struct r8192_priv *priv)

1942

1108

{

1943

struct r8192_priv *priv = ieee80211_priv(dev);

1944

1109

/* 2007/10/05 MH Disable DIG scheme now. Not tested. */

1945

1110

dm_digtable.dig_enable_flag = true;

1946

1111

dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;

1974

1139

* gain according to different threshold. BB team provide the

1975

1140

* suggested solution.

1976

1141

1977

static void dm_ctrl_initgain_byrssi(struct net_device *dev)

1142

static void dm_ctrl_initgain_byrssi(struct r8192_priv *priv)

1978

1143

{

1979

1980

1144

if (dm_digtable.dig_enable_flag == false)

1981

1145

return;

1982

1146

1983

1147

if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)

1984

dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);

1148

dm_ctrl_initgain_byrssi_by_fwfalse_alarm(priv);

1985

1149

else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)

1986

dm_ctrl_initgain_byrssi_by_driverrssi(dev);

1150

dm_ctrl_initgain_byrssi_by_driverrssi(priv);

1987

1151

}

1988

1152

1989

1153

1990

static void dm_ctrl_initgain_byrssi_by_driverrssi(

1991

struct net_device *dev)

1154

static void dm_ctrl_initgain_byrssi_by_driverrssi(struct r8192_priv *priv)

1992

1155

{

1993

struct r8192_priv *priv = ieee80211_priv(dev);

1994

1156

u8 i;

1995

1157

static u8 fw_dig=0;

1996

1158

1997

1159

if (dm_digtable.dig_enable_flag == false)

1998

1160

return;

1999

1161

2000

//DbgPrint("Dig by Sw Rssi \n");

2001

1162

if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig.

2002

1163

fw_dig = 0;

2003

1164

if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled

2004

1165

{// FW DIG Off

2005

1166

for(i=0; i<3; i++)

2006

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.

1167

rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.

2007

1168

fw_dig++;

2008

1169

dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.

2009

1170

}

2013

1174

else

2014

1175

dm_digtable.cur_connect_state = DIG_DISCONNECT;

2015

1176

2016

//DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",

2017

//DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);

2018

2019

1177

if(dm_digtable.dbg_mode == DM_DBG_OFF)

2020

1178

dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;

2021

//DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);

2022

dm_initial_gain(dev);

2023

dm_pd_th(dev);

2024

dm_cs_ratio(dev);

1179

1180

dm_initial_gain(priv);

1181

dm_pd_th(priv);

1182

dm_cs_ratio(priv);

2025

1183

if(dm_digtable.dig_algorithm_switch)

2026

1184

dm_digtable.dig_algorithm_switch = 0;

2027

1185

dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;

2028

1186

2029

1187

}

2030

1188

2031

static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(

2032

struct net_device *dev)

1189

static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct r8192_priv *priv)

2033

1190

{

2034

struct r8192_priv *priv = ieee80211_priv(dev);

2035

1191

static u32 reset_cnt = 0;

2036

1192

u8 i;

2037

1193

2043

1199

dm_digtable.dig_state = DM_STA_DIG_MAX;

2044

1200

// Fw DIG On.

2045

1201

for(i=0; i<3; i++)

2046

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.

1202

rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.

2047

1203

dm_digtable.dig_algorithm_switch = 0;

2048

1204

}

2049

1205

2056

1212

{

2057

1213

return;

2058

1214

}

2059

//DbgPrint("Dig by Fw False Alarm\n");

2060

//if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)

2061

/*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",

2062

pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,

2063

DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/

1215

2064

1216

/* 1. When RSSI decrease, We have to judge if it is smaller than a threshold

2065

1217

and then execute below step. */

2066

1218

if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))

2082

1234

dm_digtable.dig_state = DM_STA_DIG_OFF;

2083

1235

2084

1236

// 1.1 DIG Off.

2085

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.

1237

rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.

2086

1238

2087

1239

// 1.2 Set initial gain.

2088

write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);

2089

write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);

2090

write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);

2091

write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);

1240

write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x17);

1241

write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x17);

1242

write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x17);

1243

write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x17);

2092

1244

2093

1245

// 1.3 Lower PD_TH for OFDM.

2094

1246

if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)

2095

1247

{

2096

1248

/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */

2097

1249

// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.

2098

#ifdef RTL8190P

2099

write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);

2100

#else

2101

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);

2102

#endif

2103

/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2104

write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);

2105

2106

//else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)

2107

2108

2109

//else

2110

//PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);

1250

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);

2111

1251

}

2112

1252

else

2113

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

1253

write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);

2114

1254

2115

1255

// 1.4 Lower CS ratio for CCK.

2116

write_nic_byte(dev, 0xa0a, 0x08);

1256

write_nic_byte(priv, 0xa0a, 0x08);

2117

1257

2118

1258

// 1.5 Higher EDCCA.

2119

1259

//PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);

2130

1270

if (dm_digtable.dig_state == DM_STA_DIG_ON &&

2131

1271

(priv->reset_count == reset_cnt))

2132

1272

{

2133

dm_ctrl_initgain_byrssi_highpwr(dev);

1273

dm_ctrl_initgain_byrssi_highpwr(priv);

2134

1274

return;

2135

1275

}

2136

1276

else

2142

1282

}

2143

1283

2144

1284

dm_digtable.dig_state = DM_STA_DIG_ON;

2145

//DbgPrint("DIG ON\n\r");

2146

1285

2147

1286

// 2.1 Set initial gain.

2148

1287

// 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.

2149

1288

if (reset_flag == 1)

2150

1289

{

2151

write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);

2152

write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);

2153

write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);

2154

write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);

1290

write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x2c);

1291

write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x2c);

1292

write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x2c);

1293

write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x2c);

2155

1294

}

2156

1295

else

2157

1296

{

2158

write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);

2159

write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);

2160

write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);

2161

write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);

1297

write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x20);

1298

write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x20);

1299

write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x20);

1300

write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x20);

2162

1301

}

2163

1302

2164

1303

// 2.2 Higher PD_TH for OFDM.

2166

1305

{

2167

1306

/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */

2168

1307

// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.

2169

#ifdef RTL8190P

2170

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

2171

#else

2172

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);

2173

#endif

2174

2175

else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2176

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

2177

2178

//else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)

2179

2180

//else

2181

//PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);

1308

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);

2182

1309

}

2183

1310

else

2184

write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);

1311

write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);

2185

1312

2186

1313

// 2.3 Higher CS ratio for CCK.

2187

write_nic_byte(dev, 0xa0a, 0xcd);

1314

write_nic_byte(priv, 0xa0a, 0xcd);

2188

1315

2189

1316

// 2.4 Lower EDCCA.

2190

1317

/* 2008/01/11 MH 90/92 series are the same. */

2191

1318

//PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);

2192

1319

2193

1320

// 2.5 DIG On.

2194

rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.

1321

rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.

2195

1322

2196

1323

}

2197

1324

2198

dm_ctrl_initgain_byrssi_highpwr(dev);

1325

dm_ctrl_initgain_byrssi_highpwr(priv);

2199

1326

2200

1327

}

2201

1328

2202

static void dm_ctrl_initgain_byrssi_highpwr(

2203

struct net_device * dev)

1329

static void dm_ctrl_initgain_byrssi_highpwr(struct r8192_priv *priv)

2204

1330

{

2205

struct r8192_priv *priv = ieee80211_priv(dev);

2206

1331

static u32 reset_cnt_highpwr = 0;

2207

1332

2208

1333

// For smooth, we can not change high power DIG state in the range.

2226

1351

// 3.1 Higher PD_TH for OFDM for high power state.

2227

1352

if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)

2228

1353

{

2229

#ifdef RTL8190P

2230

write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);

2231

#else

2232

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);

2233

#endif

2234

2235

/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2236

write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);

2237

2238

1354

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);

2239

1355

}

2240

1356

else

2241

write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);

1357

write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);

2242

1358

}

2243

1359

else

2244

1360

{

2254

1370

// 3.2 Recover PD_TH for OFDM for normal power region.

2255

1371

if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)

2256

1372

{

2257

#ifdef RTL8190P

2258

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

2259

#else

2260

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);

2261

#endif

2262

/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2263

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

2264

2265

1373

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);

2266

1374

}

2267

1375

else

2268

write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);

1376

write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);

2269

1377

}

2270

1378

}

2271

1379

2274

1382

}

2275

1383

2276

1384

2277

static void dm_initial_gain(

2278

struct net_device * dev)

1385

static void dm_initial_gain(struct r8192_priv *priv)

2279

1386

{

2280

struct r8192_priv *priv = ieee80211_priv(dev);

2281

1387

u8 initial_gain=0;

2282

1388

static u8 initialized=0, force_write=0;

2283

1389

static u32 reset_cnt=0;

2312

1418

dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];

2313

1419

dm_digtable.pre_ig_value = 0;

2314

1420

}

2315

//DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);

2316

1421

2317

1422

// if silent reset happened, we should rewrite the values back

2318

1423

if(priv->reset_count != reset_cnt)

2321

1426

reset_cnt = priv->reset_count;

2322

1427

}

2323

1428

2324

if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))

1429

if(dm_digtable.pre_ig_value != read_nic_byte(priv, rOFDM0_XAAGCCore1))

2325

1430

force_write = 1;

2326

1431

2327

1432

{

2329

1434

|| !initialized || force_write)

2330

1435

{

2331

1436

initial_gain = (u8)dm_digtable.cur_ig_value;

2332

//DbgPrint("Write initial gain = 0x%x\n", initial_gain);

2333

1437

// Set initial gain.

2334

write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);

2335

write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);

2336

write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);

2337

write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);

1438

write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);

1439

write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);

1440

write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);

1441

write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);

2338

1442

dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;

2339

1443

initialized = 1;

2340

1444

force_write = 0;

2342

1446

}

2343

1447

}

2344

1448

2345

static void dm_pd_th(

2346

struct net_device * dev)

1449

static void dm_pd_th(struct r8192_priv *priv)

2347

1450

{

2348

struct r8192_priv *priv = ieee80211_priv(dev);

2349

1451

static u8 initialized=0, force_write=0;

2350

1452

static u32 reset_cnt = 0;

2351

1453

2390

1492

if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||

2391

1493

(initialized<=3) || force_write)

2392

1494

{

2393

//DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);

2394

1495

if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)

2395

1496

{

2396

1497

// Lower PD_TH for OFDM.

2398

1499

{

2399

1500

/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */

2400

1501

// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.

2401

#ifdef RTL8190P

2402

write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);

2403

#else

2404

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);

2405

#endif

2406

/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2407

write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);

2408

1502

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);

2409

1503

}

2410

1504

else

2411

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

1505

write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);

2412

1506

}

2413

1507

else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)

2414

1508

{

2417

1511

{

2418

1512

/* 2008/01/11 MH 40MHZ 90/92 register are not the same. */

2419

1513

// 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.

2420

#ifdef RTL8190P

2421

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

2422

#else

2423

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);

2424

#endif

2425

/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2426

write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);

2427

1514

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);

2428

1515

}

2429

1516

else

2430

write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);

1517

write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);

2431

1518

}

2432

1519

else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)

2433

1520

{

2434

1521

// Higher PD_TH for OFDM for high power state.

2435

1522

if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)

2436

1523

{

2437

#ifdef RTL8190P

2438

write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);

2439

#else

2440

write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);

2441

#endif

2442

/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)

2443

write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);

2444

1524

write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);

2445

1525

}

2446

1526

else

2447

write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);

1527

write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);

2448

1528

}

2449

1529

dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;

2450

1530

if(initialized <= 3)

2454

1534

}

2455

1535

}

2456

1536

2457

static void dm_cs_ratio(

2458

struct net_device * dev)

1537

static void dm_cs_ratio(struct r8192_priv *priv)

2459

1538

{

2460

struct r8192_priv *priv = ieee80211_priv(dev);

2461

1539

static u8 initialized=0,force_write=0;

2462

1540

static u32 reset_cnt = 0;

2463

1541

2499

1577

if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||

2500

1578

!initialized || force_write)

2501

1579

{

2502

//DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);

2503

1580

if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)

2504

1581

{

2505

1582

// Lower CS ratio for CCK.

2506

write_nic_byte(dev, 0xa0a, 0x08);

1583

write_nic_byte(priv, 0xa0a, 0x08);

2507

1584

}

2508

1585

else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)

2509

1586

{

2510

1587

// Higher CS ratio for CCK.

2511

write_nic_byte(dev, 0xa0a, 0xcd);

1588

write_nic_byte(priv, 0xa0a, 0xcd);

2512

1589

}

2513

1590

dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;

2514

1591

initialized = 1;

2516

1593

}

2517

1594

}

2518

1595

2519

void dm_init_edca_turbo(struct net_device *dev)

1596

void dm_init_edca_turbo(struct r8192_priv *priv)

2520

1597

{

2521

struct r8192_priv *priv = ieee80211_priv(dev);

2522

1598

2523

1599

priv->bcurrent_turbo_EDCA = false;

2524

1600

priv->ieee80211->bis_any_nonbepkts = false;

2525

1601

priv->bis_cur_rdlstate = false;

2526

1602

}

2527

1603

2528

#if 1

2529

static void dm_check_edca_turbo(

2530

struct net_device * dev)

1604

static void dm_check_edca_turbo(struct r8192_priv *priv)

2531

1605

{

2532

struct r8192_priv *priv = ieee80211_priv(dev);

2533

1606

PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;

2534

1607

//PSTA_QOS pStaQos = pMgntInfo->pStaQos;

2535

1608

2543

1616

// Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters

2544

1617

// should follow the settings from QAP. By Bruce, 2007-12-07.

2545

1618

2546

#if 1

2547

1619

if(priv->ieee80211->state != IEEE80211_LINKED)

2548

1620

goto dm_CheckEdcaTurbo_EXIT;

2549

#endif

2550

1621

// We do not turn on EDCA turbo mode for some AP that has IOT issue

2551

1622

if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)

2552

1623

goto dm_CheckEdcaTurbo_EXIT;

2553

1624

2554

// printk("========>%s():bis_any_nonbepkts is %d\n",__FUNCTION__,priv->bis_any_nonbepkts);

2555

1625

// Check the status for current condition.

2556

1626

if(!priv->ieee80211->bis_any_nonbepkts)

2557

1627

{

2560

1630

// For RT-AP, we needs to turn it on when Rx>Tx

2561

1631

if(curRxOkCnt > 4*curTxOkCnt)

2562

1632

{

2563

//printk("%s():curRxOkCnt > 4*curTxOkCnt\n");

2564

1633

if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)

2565

1634

{

2566

write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);

1635

write_nic_dword(priv, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);

2567

1636

priv->bis_cur_rdlstate = true;

2568

1637

}

2569

1638

}

2570

1639

else

2571

1640

{

2572

2573

//printk("%s():curRxOkCnt < 4*curTxOkCnt\n");

2574

1641

if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)

2575

1642

{

2576

write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);

1643

write_nic_dword(priv, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);

2577

1644

priv->bis_cur_rdlstate = false;

2578

1645

}

2579

1646

2597

1664

u8 mode = priv->ieee80211->mode;

2598

1665

2599

1666

// For Each time updating EDCA parameter, reset EDCA turbo mode status.

2600

dm_init_edca_turbo(dev);

1667

dm_init_edca_turbo(priv);

2601

1668

u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;

2602

1669

u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|

2603

1670

(((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|

2605

1672

((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));

2606

1673

printk("===>u4bAcParam:%x, ", u4bAcParam);

2607

1674

//write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);

2608

write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);

1675

write_nic_dword(priv, EDCAPARA_BE, u4bAcParam);

2609

1676

2610

1677

// Check ACM bit.

2611

1678

// If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.

2613

1680

// TODO: Modified this part and try to set acm control in only 1 IO processing!!

2614

1681

2615

1682

PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);

2616

u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );

1683

u8 AcmCtrl = read_nic_byte(priv, AcmHwCtrl );

2617

1684

if( pAciAifsn->f.ACM )

2618

1685

{ // ACM bit is 1.

2619

1686

AcmCtrl |= AcmHw_BeqEn;

2624

1691

}

2625

1692

2626

1693

RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;

2627

write_nic_byte(dev, AcmHwCtrl, AcmCtrl );

1694

write_nic_byte(priv, AcmHwCtrl, AcmCtrl );

2628

1695

}

2629

1696

}

2630

1697

priv->bcurrent_turbo_EDCA = false;

2638

1705

lastTxOkCnt = priv->stats.txbytesunicast;

2639

1706

lastRxOkCnt = priv->stats.rxbytesunicast;

2640

1707

}

2641

#endif

2642

1708

2643

static void dm_init_ctstoself(struct net_device * dev)

1709

static void dm_init_ctstoself(struct r8192_priv *priv)

2644

1710

{

2645

struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);

2646

2647

1711

priv->ieee80211->bCTSToSelfEnable = TRUE;

2648

1712

priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;

2649

1713

}

2650

1714

2651

static void dm_ctstoself(struct net_device *dev)

1715

static void dm_ctstoself(struct r8192_priv *priv)

2652

1716

{

2653

struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);

2654

1717

PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;

2655

1718

static unsigned long lastTxOkCnt = 0;

2656

1719

static unsigned long lastRxOkCnt = 0;

2675

1738

if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self

2676

1739

{

2677

1740

pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;

2678

//DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");

2679

1741

}

2680

1742

else //uplink

2681

1743

{

2682

#if 1

2683

1744

pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;

2684

#else

2685

if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self

2686

{

2687

pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;

2688

//DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");

2689

}

2690

else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self

2691

{

2692

pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;

2693

//DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");

2694

}

2695

#endif

2696

1745

}

2697

1746

2698

1747

lastTxOkCnt = priv->stats.txbytesunicast;

2703

1752

2704

1753

2705

1754

/* Copy 8187B template for 9xseries */

2706

#if 1

2707

static void dm_check_rfctrl_gpio(struct net_device * dev)

1755

static void dm_check_rfctrl_gpio(struct r8192_priv *priv)

2708

1756

{

2709

#ifdef RTL8192E

2710

struct r8192_priv *priv = ieee80211_priv(dev);

2711

#endif

2712

1757

2713

1758

// Walk around for DTM test, we will not enable HW - radio on/off because r/w

2714

1759

// page 1 register before Lextra bus is enabled cause system fails when resuming

2715

1760

// from S4. 20080218, Emily

2716

1761

2717

1762

// Stop to execute workitem to prevent S3/S4 bug.

2718

#ifdef RTL8190P

2719

return;

2720

#endif

2721

#ifdef RTL8192U

2722

return;

2723

#endif

2724

#ifdef RTL8192E

2725

queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);

2726

#endif

2727

2728

}

2729

2730

#endif

2731

/* Check if PBC button is pressed. */

2732

static void dm_check_pbc_gpio(struct net_device *dev)

2733

{

2734

#ifdef RTL8192U

2735

struct r8192_priv *priv = ieee80211_priv(dev);

2736

u8 tmp1byte;

2737

2738

2739

tmp1byte = read_nic_byte(dev,GPI);

2740

if(tmp1byte == 0xff)

2741

return;

2742

2743

if (tmp1byte&BIT6 || tmp1byte&BIT0)

2744

{

2745

// Here we only set bPbcPressed to TRUE

2746

// After trigger PBC, the variable will be set to FALSE

2747

RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");

2748

priv->bpbc_pressed = true;

2749

}

2750

#endif

2751

2752

}

2753

2754

#ifdef RTL8192E

1763

queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);

1764

}

2755

1765

2756

1766

/* PCI will not support workitem call back HW radio on-off control. */

2757

1767

void dm_gpio_change_rf_callback(struct work_struct *work)

2758

1768

{

2759

1769

struct delayed_work *dwork = container_of(work,struct delayed_work,work);

2760

1770

struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);

2761

struct net_device *dev = priv->ieee80211->dev;

2762

1771

u8 tmp1byte;

2763

1772

RT_RF_POWER_STATE eRfPowerStateToSet;

2764

1773

bool bActuallySet = false;

2768

1777

} else {

2769

1778

// 0x108 GPIO input register is read only

2770

1779

//set 0x108 B1= 1: RF-ON; 0: RF-OFF.

2771

tmp1byte = read_nic_byte(dev,GPI);

1780

tmp1byte = read_nic_byte(priv, GPI);

2772

1781

2773

1782

eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;

2774

1783

2785

1794

2786

1795

if (bActuallySet) {

2787

1796

priv->bHwRfOffAction = 1;

2788

MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);

1797

MgntActSet_RF_State(priv, eRfPowerStateToSet, RF_CHANGE_BY_HW);

2789

1798

//DrvIFIndicateCurrentPhyStatus(pAdapter);

2790

1799

} else {

2791

1800

msleep(2000);

2793

1802

}

2794

1803

}

2795

1804

2796

#endif

2797

2798

1805

/* Check if Current RF RX path is enabled */

2799

1806

void dm_rf_pathcheck_workitemcallback(struct work_struct *work)

2800

1807

{

2801

1808

struct delayed_work *dwork = container_of(work,struct delayed_work,work);

2802

1809

struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);

2803

struct net_device *dev =priv->ieee80211->dev;

2804

//bool bactually_set = false;

2805

1810

u8 rfpath = 0, i;

2806

1811

2807

1812

2808

1813

/* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will

2809

1814

always be the same. We only read 0xc04 now. */

2810

rfpath = read_nic_byte(dev, 0xc04);

1815

rfpath = read_nic_byte(priv, 0xc04);

2811

1816

2812

1817

// Check Bit 0-3, it means if RF A-D is enabled.

2813

1818

for (i = 0; i < RF90_PATH_MAX; i++)

2820

1825

if(!DM_RxPathSelTable.Enable)

2821

1826

return;

2822

1827

2823

dm_rxpath_sel_byrssi(dev);

1828

dm_rxpath_sel_byrssi(priv);

2824

1829

}

2825

1830

2826

static void dm_init_rxpath_selection(struct net_device * dev)

1831

static void dm_init_rxpath_selection(struct r8192_priv *priv)

2827

1832

{

2828

1833

u8 i;

2829

struct r8192_priv *priv = ieee80211_priv(dev);

1834

2830

1835

DM_RxPathSelTable.Enable = 1; //default enabled

2831

1836

DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;

2832

1837

DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;

2844

1849

}

2845

1850

}

2846

1851

2847

static void dm_rxpath_sel_byrssi(struct net_device * dev)

1852

static void dm_rxpath_sel_byrssi(struct r8192_priv *priv)

2848

1853

{

2849

struct r8192_priv *priv = ieee80211_priv(dev);

2850

1854

u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;

2851

1855

u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;

2852

1856

u8 cck_default_Rx=0x2; //RF-C

2863

1867

2864

1868

if(!cck_Rx_Path_initialized)

2865

1869

{

2866

DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);

1870

DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(priv, 0xa07)&0xf);

2867

1871

cck_Rx_Path_initialized = 1;

2868

1872

}

2869

1873

2870

1874

DM_RxPathSelTable.disabledRF = 0xf;

2871

DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));

1875

DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(priv, 0xc04));

2872

1876

2873

1877

if(priv->ieee80211->mode == WIRELESS_MODE_B)

2874

1878

{

2875

1879

DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2

2876

//DbgPrint("Pure B mode, use cck rx version2 \n");

2877

1880

}

2878

1881

2879

1882

//decide max/sec/min rssi index

3067

2070

//record the enabled rssi threshold

3068

2071

DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;

3069

2072

//disable the BB Rx path, OFDM

3070

rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]

3071

rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]

2073

rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]

2074

rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]

3072

2075

disabled_rf_cnt++;

3073

2076

}

3074

2077

if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)

3083

2086

if(update_cck_rx_path)

3084

2087

{

3085

2088

DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);

3086

rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);

2089

rtl8192_setBBreg(priv, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);

3087

2090

}

3088

2091

3089

2092

if(DM_RxPathSelTable.disabledRF)

3095

2098

if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])

3096

2099

{

3097

2100

//enable the BB Rx path

3098

//DbgPrint("RF-%d is enabled. \n", 0x1<<i);

3099

rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]

3100

rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]

2101

rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]

2102

rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]

3101

2103

DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;

3102

2104

disabled_rf_cnt--;

3103

2105

}

3109

2111

3110

2112

* Call a workitem to check current RXRF path and Rx Path selection by RSSI.

3111

2113

3112

static void dm_check_rx_path_selection(struct net_device *dev)

2114

static void dm_check_rx_path_selection(struct r8192_priv *priv)

3113

2115

{

3114

struct r8192_priv *priv = ieee80211_priv(dev);

3115

2116

queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);

3116

2117

}

3117

2118

3118

static void dm_init_fsync (struct net_device *dev)

2119

static void dm_init_fsync(struct r8192_priv *priv)

3119

2120

{

3120

struct r8192_priv *priv = ieee80211_priv(dev);

3121

3122

2121

priv->ieee80211->fsync_time_interval = 500;

3123

2122

priv->ieee80211->fsync_rate_bitmap = 0x0f000800;

3124

2123

priv->ieee80211->fsync_rssi_threshold = 30;

3125

#ifdef RTL8190P

3126

priv->ieee80211->bfsync_enable = true;

3127

#else

3128

2124

priv->ieee80211->bfsync_enable = false;

3129

#endif

3130

2125

priv->ieee80211->fsync_multiple_timeinterval = 3;

3131

2126

priv->ieee80211->fsync_firstdiff_ratethreshold= 100;

3132

2127

priv->ieee80211->fsync_seconddiff_ratethreshold= 200;

3134

2129

priv->framesyncMonitor = 1; // current default 0xc38 monitor on

3135

2130

3136

2131

init_timer(&priv->fsync_timer);

3137

priv->fsync_timer.data = (unsigned long)dev;

2132

priv->fsync_timer.data = (unsigned long)priv;

3138

2133

priv->fsync_timer.function = dm_fsync_timer_callback;

3139

2134

}

3140

2135

3141

2136

3142

static void dm_deInit_fsync(struct net_device *dev)

2137

static void dm_deInit_fsync(struct r8192_priv *priv)

3143

2138

{

3144

struct r8192_priv *priv = ieee80211_priv(dev);

3145

2139

del_timer_sync(&priv->fsync_timer);

3146

2140

}

3147

2141

3148

void dm_fsync_timer_callback(unsigned long data)

2142

static void dm_fsync_timer_callback(unsigned long data)

3149

2143

{

3150

struct net_device *dev = (struct net_device *)data;

3151

struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);

2144

struct r8192_priv *priv = (struct r8192_priv *)data;

3152

2145

u32 rate_index, rate_count = 0, rate_count_diff=0;

3153

2146

bool bSwitchFromCountDiff = false;

3154

2147

bool bDoubleTimeInterval = false;

3209

2202

priv->bswitch_fsync = !priv->bswitch_fsync;

3210

2203

if(priv->bswitch_fsync)

3211

2204

{

3212

#ifdef RTL8190P

3213

write_nic_byte(dev,0xC36, 0x00);

3214

#else

3215

write_nic_byte(dev,0xC36, 0x1c);

3216

#endif

3217

write_nic_byte(dev, 0xC3e, 0x90);

2205

write_nic_byte(priv,0xC36, 0x1c);

2206

write_nic_byte(priv, 0xC3e, 0x90);

3218

2207

}

3219

2208

else

3220

2209

{

3221

#ifdef RTL8190P

3222

write_nic_byte(dev, 0xC36, 0x40);

3223

#else

3224

write_nic_byte(dev, 0xC36, 0x5c);

3225

#endif

3226

write_nic_byte(dev, 0xC3e, 0x96);

2210

write_nic_byte(priv, 0xC36, 0x5c);

2211

write_nic_byte(priv, 0xC3e, 0x96);

3227

2212

}

3228

2213

}

3229

2214

else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)

3231

2216

if(priv->bswitch_fsync)

3232

2217

{

3233

2218

priv->bswitch_fsync = false;

3234

#ifdef RTL8190P

3235

write_nic_byte(dev, 0xC36, 0x40);

3236

#else

3237

write_nic_byte(dev, 0xC36, 0x5c);

3238

#endif

3239

write_nic_byte(dev, 0xC3e, 0x96);

2219

write_nic_byte(priv, 0xC36, 0x5c);

2220

write_nic_byte(priv, 0xC3e, 0x96);

3240

2221

}

3241

2222

}

3242

2223

if(bDoubleTimeInterval){

3258

2239

if(priv->bswitch_fsync)

3259

2240

{

3260

2241

priv->bswitch_fsync = false;

3261

#ifdef RTL8190P

3262

write_nic_byte(dev, 0xC36, 0x40);

3263

#else

3264

write_nic_byte(dev, 0xC36, 0x5c);

3265

#endif

3266

write_nic_byte(dev, 0xC3e, 0x96);

2242

write_nic_byte(priv, 0xC36, 0x5c);

2243

write_nic_byte(priv, 0xC3e, 0x96);

3267

2244

}

3268

2245

priv->ContiuneDiffCount = 0;

3269

#ifdef RTL8190P

3270

write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);

3271

#else

3272

write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);

3273

#endif

2246

write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);

3274

2247

}

3275

2248

RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);

3276

2249

RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);

3277

2250

}

3278

2251

3279

static void dm_StartHWFsync(struct net_device *dev)

2252

static void dm_StartHWFsync(struct r8192_priv *priv)

3280

2253

{

3281

2254

RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);

3282

write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);

3283

write_nic_byte(dev, 0xc3b, 0x41);

2255

write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cf);

2256

write_nic_byte(priv, 0xc3b, 0x41);

3284

2257

}

3285

2258

3286

static void dm_EndSWFsync(struct net_device *dev)

2259

static void dm_EndSWFsync(struct r8192_priv *priv)

3287

2260

{

3288

struct r8192_priv *priv = ieee80211_priv(dev);

3289

3290

2261

RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);

3291

2262

del_timer_sync(&(priv->fsync_timer));

3292

2263

3295

2266

{

3296

2267

priv->bswitch_fsync = false;

3297

2268

3298

#ifdef RTL8190P

3299

write_nic_byte(dev, 0xC36, 0x40);

3300

#else

3301

write_nic_byte(dev, 0xC36, 0x5c);

3302

#endif

2269

write_nic_byte(priv, 0xC36, 0x40);

3303

2270

3304

write_nic_byte(dev, 0xC3e, 0x96);

2271

write_nic_byte(priv, 0xC3e, 0x96);

3305

2272

}

3306

2273

3307

2274

priv->ContiuneDiffCount = 0;

3308

#ifndef RTL8190P

3309

write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);

3310

#endif

3311

2275

2276

write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);

3312

2277

}

3313

2278

3314

static void dm_StartSWFsync(struct net_device *dev)

2279

static void dm_StartSWFsync(struct r8192_priv *priv)

3315

2280

{

3316

struct r8192_priv *priv = ieee80211_priv(dev);

3317

2281

u32 rateIndex;

3318

2282

u32 rateBitmap;

3319

2283

3346

2310

priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);

3347

2311

add_timer(&priv->fsync_timer);

3348

2312

3349

#ifndef RTL8190P

3350

write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);

3351

#endif

3352

2313

write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cd);

3353

2314

}

3354

2315

3355

static void dm_EndHWFsync(struct net_device *dev)

2316

static void dm_EndHWFsync(struct r8192_priv *priv)

3356

2317

{

3357

2318

RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);

3358

write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);

3359

write_nic_byte(dev, 0xc3b, 0x49);

3360

2319

write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);

2320

write_nic_byte(priv, 0xc3b, 0x49);

3361

2321

}

3362

2322

3363

void dm_check_fsync(struct net_device *dev)

2323

static void dm_check_fsync(struct r8192_priv *priv)

3364

2324

{

3365

2325

#define RegC38_Default 0

3366

2326

#define RegC38_NonFsync_Other_AP 1

3367

2327

#define RegC38_Fsync_AP_BCM 2

3368

struct r8192_priv *priv = ieee80211_priv(dev);

3369

2328

//u32 framesyncC34;

3370

2329

static u8 reg_c38_State=RegC38_Default;

3371

2330

static u32 reset_cnt=0;

3381

2340

switch(priv->ieee80211->fsync_state)

3382

2341

{

3383

2342

case Default_Fsync:

3384

dm_StartHWFsync(dev);

2343

dm_StartHWFsync(priv);

3385

2344

priv->ieee80211->fsync_state = HW_Fsync;

3386

2345

break;

3387

2346

case SW_Fsync:

3388

dm_EndSWFsync(dev);

3389

dm_StartHWFsync(dev);

2347

dm_EndSWFsync(priv);

2348

dm_StartHWFsync(priv);

3390

2349

priv->ieee80211->fsync_state = HW_Fsync;

3391

2350

break;

3392

2351

case HW_Fsync:

3399

2358

switch(priv->ieee80211->fsync_state)

3400

2359

{

3401

2360

case Default_Fsync:

3402

dm_StartSWFsync(dev);

2361

dm_StartSWFsync(priv);

3403

2362

priv->ieee80211->fsync_state = SW_Fsync;

3404

2363

break;

3405

2364

case HW_Fsync:

3406

dm_EndHWFsync(dev);

3407

dm_StartSWFsync(dev);

2365

dm_EndHWFsync(priv);

2366

dm_StartSWFsync(priv);

3408

2367

priv->ieee80211->fsync_state = SW_Fsync;

3409

2368

break;

3410

2369

case SW_Fsync:

3417

2376

{

3418

2377

if(reg_c38_State != RegC38_Fsync_AP_BCM)

3419

2378

{ //For broadcom AP we write different default value

3420

#ifdef RTL8190P

3421

write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);

3422

#else

3423

write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);

3424

#endif

2379

write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);

3425

2380

3426

2381

reg_c38_State = RegC38_Fsync_AP_BCM;

3427

2382

}

3432

2387

switch(priv->ieee80211->fsync_state)

3433

2388

{

3434

2389

case HW_Fsync:

3435

dm_EndHWFsync(dev);

2390

dm_EndHWFsync(priv);

3436

2391

priv->ieee80211->fsync_state = Default_Fsync;

3437

2392

break;

3438

2393

case SW_Fsync:

3439

dm_EndSWFsync(dev);

2394

dm_EndSWFsync(priv);

3440

2395

priv->ieee80211->fsync_state = Default_Fsync;

3441

2396

break;

3442

2397

case Default_Fsync:

3452

2407

{

3453

2408

if(reg_c38_State != RegC38_NonFsync_Other_AP)

3454

2409

{

3455

#ifdef RTL8190P

3456

write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);

3457

#else

3458

write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);

3459

#endif

2410

write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);

3460

2411

3461

2412

reg_c38_State = RegC38_NonFsync_Other_AP;

3462

#if 0//cosa

3463

if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)

3464

DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);

3465

else

3466

DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);

3467

#endif

3468

2413

}

3469

2414

}

3470

2415

else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))

3471

2416

{

3472

2417

if(reg_c38_State)

3473

2418

{

3474

write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);

2419

write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);

3475

2420

reg_c38_State = RegC38_Default;

3476

//DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);

3477

2421

}

3478

2422

}

3479

2423

}

3481

2425

{

3482

2426

if(reg_c38_State)

3483

2427

{

3484

write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);

2428

write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);

3485

2429

reg_c38_State = RegC38_Default;

3486

//DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);

3487

2430

}

3488

2431

}

3489

2432

}

3492

2435

{

3493

2436

if(priv->reset_count != reset_cnt)

3494

2437

{ //After silent reset, the reg_c38_State will be returned to default value

3495

write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);

2438

write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);

3496

2439

reg_c38_State = RegC38_Default;

3497

2440

reset_cnt = priv->reset_count;

3498

//DbgPrint("reg_c38_State = 0 for silent reset. \n");

3499

2441

}

3500

2442

}

3501

2443

else

3502

2444

{

3503

2445

if(reg_c38_State)

3504

2446

{

3505

write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);

2447

write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);

3506

2448

reg_c38_State = RegC38_Default;

3507

//DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);

3508

2449

}

3509

2450

}

3510

2451

}

3513

2454

* Detect Signal strength to control TX Registry

3514

2455

* Tx Power Control For Near/Far Range

3515

2456

3516

static void dm_init_dynamic_txpower(struct net_device *dev)

2457

static void dm_init_dynamic_txpower(struct r8192_priv *priv)

3517

2458

{

3518

struct r8192_priv *priv = ieee80211_priv(dev);

3519

3520

2459

//Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.

3521

2460

priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control

3522

2461

priv->bLastDTPFlag_High = false;

3525

2464

priv->bDynamicTxLowPower = false;

3526

2465

}

3527

2466

3528

static void dm_dynamic_txpower(struct net_device *dev)

2467

static void dm_dynamic_txpower(struct r8192_priv *priv)

3529

2468

{

3530

struct r8192_priv *priv = ieee80211_priv(dev);

3531

2469

unsigned int txhipower_threshhold=0;

3532

2470

unsigned int txlowpower_threshold=0;

3533

2471

if(priv->ieee80211->bdynamic_txpower_enable != true)

3536

2474

priv->bDynamicTxLowPower = false;

3537

2475

return;

3538

2476

}

3539

//printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);

3540

2477

if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){

3541

2478

txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;

3542

2479

txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;

3547

2484

txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;

3548

2485

}

3549

2486

3550

// printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);

3551

3552

RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);

2487

RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n" , priv->undecorated_smoothed_pwdb);

3553

2488

3554

2489

if(priv->ieee80211->state == IEEE80211_LINKED)

3555

2490

{

3586

2521

if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||

3587

2522

(priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )

3588

2523

{

3589

RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);

3590

3591

3592

rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);

2524

RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d\n", priv->ieee80211->current_network.channel);

2525

2526

2527

rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel);

3593

2528

3594

2529

}

3595

2530

priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;

3598

2533

}

3599

2534

3600

2535

//added by vivi, for read tx rate and retrycount

3601

static void dm_check_txrateandretrycount(struct net_device * dev)

2536

static void dm_check_txrateandretrycount(struct r8192_priv *priv)

3602

2537

{

3603

struct r8192_priv *priv = ieee80211_priv(dev);

3604

2538

struct ieee80211_device* ieee = priv->ieee80211;

3605

//for 11n tx rate

3606

// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);

3607

ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);

3608

//printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);

2539

3609

2540

//for initial tx rate

3610

// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);

3611

ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);

2541

ieee->softmac_stats.last_packet_rate = read_nic_byte(priv ,Initial_Tx_Rate_Reg);

3612

2542

//for tx tx retry count

3613

// priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);

3614

ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);

2543

ieee->softmac_stats.txretrycount = read_nic_dword(priv, Tx_Retry_Count_Reg);

3615

2544

}

3616

2545

3617

static void dm_send_rssi_tofw(struct net_device *dev)

2546

static void dm_send_rssi_tofw(struct r8192_priv *priv)

3618

2547

{

3619

DCMD_TXCMD_T tx_cmd;

3620

struct r8192_priv *priv = ieee80211_priv(dev);

3621

3622

2548

// If we test chariot, we should stop the TX command ?

3623

2549

// Because 92E will always silent reset when we send tx command. We use register

3624

2550

// 0x1e0(byte) to botify driver.

3625

write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);

2551

write_nic_byte(priv, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);

3626

2552

return;

3627

#if 1

3628

tx_cmd.Op = TXCMD_SET_RX_RSSI;

3629

tx_cmd.Length = 4;

3630

tx_cmd.Value = priv->undecorated_smoothed_pwdb;

3631

3632

cmpk_message_handle_tx(dev, (u8*)&tx_cmd,

3633

DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));

3634

#endif

3635

2553

}

3636

2554

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