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Viewing changes to drivers/ata/pata_hpt37x.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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drivers/ata/pata_hpt37x.c
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 *      Look into engine reset on timeout errors. Should not be required.
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/libata.h>
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#define DRV_NAME        "pata_hpt37x"
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#define DRV_VERSION     "0.6.22"
 
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#define DRV_VERSION     "0.6.23"
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struct hpt_clock {
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        u8      xfer_speed;
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        while (list[i] != NULL) {
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                if (!strcmp(list[i], model_num)) {
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                        pr_warning(DRV_NAME ": %s is not supported for %s.\n",
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                                   modestr, list[i]);
 
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                        pr_warn("%s is not supported for %s\n",
 
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                                modestr, list[i]);
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                        return 1;
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                }
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                i++;
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                        chip_table = &hpt372;
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                        break;
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                default:
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                        pr_err(DRV_NAME ": Unknown HPT366 subtype, "
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                               "please report (%d).\n", rev);
 
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                        pr_err("Unknown HPT366 subtype, please report (%d)\n",
 
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                               rev);
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                        return -ENODEV;
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                }
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                break;
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                        *ppi = &info_hpt374_fn1;
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                break;
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        default:
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                pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n",
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                       dev->device);
 
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                pr_err("PCI table is bogus, please report (%d)\n", dev->device);
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                return -ENODEV;
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        }
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        /* Ok so this is a chip we support */
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                u8 sr;
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                u32 total = 0;
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                pr_warning(DRV_NAME ": BIOS has not set timing clocks.\n");
 
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                pr_warn("BIOS has not set timing clocks\n");
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                /* This is the process the HPT371 BIOS is reported to use */
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                for (i = 0; i < 128; i++) {
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                                               (f_high << 16) | f_low | 0x100);
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                }
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                if (adjust == 8) {
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                        pr_err(DRV_NAME ": DPLL did not stabilize!\n");
 
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                        pr_err("DPLL did not stabilize!\n");
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                        return -ENODEV;
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                }
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                if (dpll == 3)
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                else
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                        private_data = (void *)hpt37x_timings_50;
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                pr_info(DRV_NAME ": bus clock %dMHz, using %dMHz DPLL.\n",
 
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                pr_info("bus clock %dMHz, using %dMHz DPLL\n",
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                        MHz[clock_slot], MHz[dpll]);
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        } else {
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                private_data = (void *)chip_table->clocks[clock_slot];
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                if (clock_slot < 2 && ppi[0] == &info_hpt370a)
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                        ppi[0] = &info_hpt370a_33;
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                pr_info(DRV_NAME ": %s using %dMHz bus clock.\n",
 
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                pr_info("%s using %dMHz bus clock\n",
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                        chip_table->name, MHz[clock_slot]);
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        }
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