14
#define ROM_OFFSET 0x10C00000
15
#define STACK_GAURD 0x10
21
movew #0x2700, %sr /* Exceptions off! */
24
/* Init chip registers. uCsimm specific */
25
moveb #0x00, 0xfffffb0b /* Watchdog off */
26
moveb #0x10, 0xfffff000 /* SCR */
28
movew #0x2400, 0xfffff200 /* PLLCR */
29
movew #0x0123, 0xfffff202 /* PLLFSR */
31
moveb #0x00, 0xfffff40b /* enable chip select */
32
moveb #0x00, 0xfffff423 /* enable /DWE */
33
moveb #0x08, 0xfffffd0d /* disable hardmap */
34
moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
36
movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
37
movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
39
movew #0x8f00, 0xfffffc00 /* DRAM configuration */
40
movew #0x9667, 0xfffffc02 /* DRAM control */
41
movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
42
movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
44
moveb #0x40, 0xfffff300 /* IVR */
45
movel #0x007FFFFF, %d0 /* IMR */
52
moveb #0x08, 0xfffff907 /* Ignore CTS */
53
movew #0x010b, 0xfffff902 /* BAUD to 9600 */
54
movew #0xe100, 0xfffff900 /* enable */
57
movew #16384, %d0 /* PLL settle wait loop */
62
moveq #70, %d7 /* 'F' */
63
moveb %d7,0xfffff907 /* No absolute addresses */
71
moveq #82, %d7 /* 'R' */
72
moveb %d7,0xfffff907 /* No absolute addresses */
78
moveal #0x007ffff0, %ssp
82
/* Copy 0 to %a0 until %a0 >= %a1 */
89
moveq #67, %d7 /* 'C' */
99
moveq #70, %d7 /* 'F' */
118
movew 0xfffff906, %d7
127
* Set up the usable of RAM stuff. Size of RAM is determined then
128
* an initial stack set up at the end.