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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2010 Intel Corporation.
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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#define IXGBE_82598_RAR_ENTRIES 16
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#define IXGBE_82598_MC_TBL_SIZE 128
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#define IXGBE_82598_VFT_TBL_SIZE 128
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#define IXGBE_82598_RX_PB_SIZE 512
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static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
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ixgbe_link_speed speed,
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* @hw: pointer to hardware structure
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* Starts the hardware using the generic start_hw function.
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* Then set pcie completion timeout
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* Disables relaxed ordering Then set pcie completion timeout
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static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
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ret_val = ixgbe_start_hw_generic(hw);
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/* Disable relaxed ordering */
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for (i = 0; ((i < hw->mac.max_tx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
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regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
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for (i = 0; ((i < hw->mac.max_rx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
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regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
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IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
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hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE;
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/* set the completion timeout for interface */
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if (ret_val == 0)
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ixgbe_set_pcie_completion_timeout(hw);
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enum ixgbe_media_type media_type;
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/* Detect if there is a copper PHY attached. */
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switch (hw->phy.type) {
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case ixgbe_phy_cu_unknown:
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media_type = ixgbe_media_type_copper;
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/* Media type for I82598 is based on device ID */
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switch (hw->device_id) {
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case IXGBE_DEV_ID_82598:
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case IXGBE_DEV_ID_82598_BX:
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/* Default device ID is mezzanine card KX/KX4 */
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media_type = ixgbe_media_type_backplane;
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case IXGBE_DEV_ID_82598AF_DUAL_PORT:
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* 2: Tx flow control is enabled (we can send pause frames but
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* we do not support receiving pause frames).
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* 3: Both Rx and Tx flow control (symmetric) are enabled.
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#ifdef CONFIG_DCB
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* 4: Priority Flow Control is enabled.
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switch (hw->fc.current_mode) {
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case ixgbe_fc_none:
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reg = (rx_pba_size - hw->fc.low_water) << 6;
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if (hw->fc.send_xon)
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reg |= IXGBE_FCRTL_XONE;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
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reg = (rx_pba_size - hw->fc.high_water) << 10;
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reg = (rx_pba_size - hw->fc.high_water) << 6;
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reg |= IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
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* ixgbe_setup_mac_link_82598 - Set MAC link speed
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* @hw: pointer to hardware structure
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* @speed: new link speed
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* @autoneg: true if auto-negotiation enabled
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* @autoneg_wait_to_complete: true if waiting is needed to complete
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* @autoneg_wait_to_complete: true when waiting for completion is needed
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* Set the link speed in the AUTOC register and restarts link.
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* ixgbe_hw This will write the AUTOC register based on the new
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status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
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status = ixgbe_start_mac_link_82598(hw,
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autoneg_wait_to_complete);
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/* Setup the PHY according to input speed */
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status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
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autoneg_wait_to_complete);
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ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
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* Prevent the PCI-E bus from from hanging by disabling PCI-E master
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* access and verify no pending requests before reset
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status = ixgbe_disable_pcie_master(hw);
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status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
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hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
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ixgbe_disable_pcie_master(hw);
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* Issue global reset to the MAC. This needs to be a SW reset.
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* If link reset is used, it might reset the MAC when mng is using it
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hw_dbg(hw, "Reset polling failed to complete.\n");
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* Double resets are required for recovery from certain error
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* conditions. Between resets, it is necessary to stall to allow time
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* for any pending HW events to complete. We use 1usec since that is
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* what is needed for ixgbe_disable_pcie_master(). The second reset
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* then clears out any effects of those events.
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if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
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hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
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gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
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/* Store the permanent mac address */
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hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
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* Store MAC address from RAR0, clear receive address registers, and
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* clear the multicast table
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hw->mac.ops.init_rx_addrs(hw);
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/* Store the permanent mac address */
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hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
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status = phy_status;
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static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
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u32 rar_entries = hw->mac.num_rar_entries;
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/* Make sure we are using a valid rar index range */
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if (rar >= rar_entries) {
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hw_dbg(hw, "RAR index %d is out of range.\n", rar);
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return IXGBE_ERR_INVALID_ARGUMENT;
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rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
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rar_high &= ~IXGBE_RAH_VIND_MASK;
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u32 rar_entries = hw->mac.num_rar_entries;
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if (rar < rar_entries) {
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rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
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if (rar_high & IXGBE_RAH_VIND_MASK) {
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rar_high &= ~IXGBE_RAH_VIND_MASK;
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IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
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/* Make sure we are using a valid rar index range */
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if (rar >= rar_entries) {
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hw_dbg(hw, "RAR index %d is out of range.\n", rar);
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return IXGBE_ERR_INVALID_ARGUMENT;
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rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
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if (rar_high & IXGBE_RAH_VIND_MASK) {
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rar_high &= ~IXGBE_RAH_VIND_MASK;
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IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
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* ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
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* over I2C interface through an intermediate phy.
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* ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
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* @hw: pointer to hardware structure
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* @byte_offset: EEPROM byte offset to read
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* @eeprom_data: value read
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* Performs byte read operation to SFP module's EEPROM over I2C interface.
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* Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
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static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *eeprom_data)
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sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
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usleep_range(10000, 20000);
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
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/* Copper PHY must be checked before AUTOC LMS to determine correct
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* physical layer because 10GBase-T PHYs use LMS = KX4/KX */
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if (hw->phy.type == ixgbe_phy_tn ||
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hw->phy.type == ixgbe_phy_cu_unknown) {
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hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
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switch (hw->phy.type) {
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case ixgbe_phy_cu_unknown:
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hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE,
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MDIO_MMD_PMAPMD, &ext_ability);
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if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
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physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
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if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
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return physical_layer;
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* ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
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* @hw: pointer to the HW structure
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* Calls common function and corrects issue with some single port devices
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* that enable LAN1 but not LAN0.
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static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
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struct ixgbe_bus_info *bus = &hw->bus;
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ixgbe_set_lan_id_multi_port_pcie(hw);
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/* check if LAN0 is disabled */
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hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
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if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
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hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
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/* if LAN0 is completely disabled force function to 0 */
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if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
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!(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
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!(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
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static struct ixgbe_mac_operations mac_ops_82598 = {
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.init_hw = &ixgbe_init_hw_generic,
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.reset_hw = &ixgbe_reset_hw_82598,
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.get_mac_addr = &ixgbe_get_mac_addr_generic,
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.stop_adapter = &ixgbe_stop_adapter_generic,
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.get_bus_info = &ixgbe_get_bus_info_generic,
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.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
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.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
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.read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
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.write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
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.setup_link = &ixgbe_setup_mac_link_82598,
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.set_vmdq = &ixgbe_set_vmdq_82598,
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.clear_vmdq = &ixgbe_clear_vmdq_82598,
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.init_rx_addrs = &ixgbe_init_rx_addrs_generic,
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.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
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.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
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.enable_mc = &ixgbe_enable_mc_generic,
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.disable_mc = &ixgbe_disable_mc_generic,
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.clear_vfta = &ixgbe_clear_vfta_82598,
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.set_vfta = &ixgbe_set_vfta_82598,
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.fc_enable = &ixgbe_fc_enable_82598,
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.acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
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.release_swfw_sync = &ixgbe_release_swfw_sync,
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static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
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.init_params = &ixgbe_init_eeprom_params_generic,
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.read = &ixgbe_read_eerd_generic,
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.read_buffer = &ixgbe_read_eerd_buffer_generic,
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.calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
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.validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
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.update_checksum = &ixgbe_update_eeprom_checksum_generic,