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#define SPEAR300_TELECOM_BASE UL(0x50000000)
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22
/* Interrupt registers offsets and masks */
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#define INT_ENB_MASK_REG 0x54
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#define INT_STS_MASK_REG 0x58
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#define IT_PERS_S_IRQ_MASK (1 << 0)
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#define IT_CHANGE_S_IRQ_MASK (1 << 1)
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#define I2S_IRQ_MASK (1 << 2)
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#define TDM_IRQ_MASK (1 << 3)
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#define CAMERA_L_IRQ_MASK (1 << 4)
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#define CAMERA_F_IRQ_MASK (1 << 5)
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#define CAMERA_V_IRQ_MASK (1 << 6)
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#define KEYBOARD_IRQ_MASK (1 << 7)
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#define GPIO1_IRQ_MASK (1 << 8)
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#define SPEAR300_INT_ENB_MASK_REG 0x54
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#define SPEAR300_INT_STS_MASK_REG 0x58
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#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
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#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
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#define SPEAR300_I2S_IRQ_MASK (1 << 2)
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#define SPEAR300_TDM_IRQ_MASK (1 << 3)
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#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
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#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
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#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
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#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
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#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
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#define SHIRQ_RAS1_MASK 0x1FF
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#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
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#define SPEAR300_CLCD_BASE UL(0x60000000)
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#define SPEAR300_SDHCI_BASE UL(0x70000000)