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Viewing changes to arch/arm/plat-samsung/irq-vic-timer.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/plat-samsung/irq-vic-timer.c
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}
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/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
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static void s3c_irq_timer_mask(struct irq_data *data)
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{
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        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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        u32 mask = (u32)data->chip_data;
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        reg &= 0x1f;  /* mask out pending interrupts */
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        reg &= ~mask;
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        __raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_unmask(struct irq_data *data)
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{
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        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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        u32 mask = (u32)data->chip_data;
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        reg &= 0x1f;  /* mask out pending interrupts */
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        reg |= mask;
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        __raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_ack(struct irq_data *data)
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{
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        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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        u32 mask = (u32)data->chip_data;
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        reg &= 0x1f;
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        reg |= mask << 5;
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        __raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static struct irq_chip s3c_irq_timer = {
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        .name           = "s3c-timer",
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        .irq_mask       = s3c_irq_timer_mask,
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        .irq_unmask     = s3c_irq_timer_unmask,
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        .irq_ack        = s3c_irq_timer_ack,
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};
 
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static void s3c_irq_timer_ack(struct irq_data *d)
 
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{
 
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        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 
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        u32 mask = (1 << 5) << (d->irq - gc->irq_base);
 
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        irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
 
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}
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/**
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 * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
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 * @parent_irq: The parent IRQ on the VIC for the timer.
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 * @timer_irq: The IRQ to be used for the timer.
 
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 * @num: Number of timers to initialize
 
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 * @timer_irq: Base IRQ number to be used for the timers.
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 *
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 * Register the necessary IRQ chaining and support for the timer IRQs
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 * chained of the VIC.
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 */
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void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
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                                   unsigned int timer_irq)
 
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void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
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{
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        struct irq_desc *desc = irq_to_desc(parent_irq);
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        set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
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        set_irq_chip(timer_irq, &s3c_irq_timer);
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        set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
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        set_irq_handler(timer_irq, handle_level_irq);
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        set_irq_flags(timer_irq, IRQF_VALID);
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        desc->irq_data.handler_data = (void *)timer_irq;
 
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        unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 
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                                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
 
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        struct irq_chip_generic *s3c_tgc;
 
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        struct irq_chip_type *ct;
 
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        unsigned int i;
 
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        s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
 
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                                         S3C64XX_TINT_CSTAT, handle_level_irq);
 
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        if (!s3c_tgc) {
 
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                pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
 
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                       __func__, timer_irq);
 
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                return;
 
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        }
 
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        ct = s3c_tgc->chip_types;
 
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        ct->chip.irq_mask = irq_gc_mask_clr_bit;
 
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        ct->chip.irq_unmask = irq_gc_mask_set_bit;
 
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        ct->chip.irq_ack = s3c_irq_timer_ack;
 
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        irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 
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                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 
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        /* Clear the upper bits of the mask_cache*/
 
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        s3c_tgc->mask_cache &= 0x1f;
 
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        for (i = 0; i < num; i++, timer_irq++) {
 
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                irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
 
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                irq_set_handler_data(pirq[i], (void *)timer_irq);
 
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        }
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}