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Viewing changes to drivers/staging/tidspbridge/core/tiomap3430_pwr.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/staging/tidspbridge/core/tiomap3430_pwr.c
29
29
/*  ----------------------------------- Platform Manager */
30
30
#include <dspbridge/brddefs.h>
31
31
#include <dspbridge/dev.h>
32
 
#include <dspbridge/iodefs.h>
 
32
#include <dspbridge/io.h>
33
33
 
34
34
/* ------------------------------------ Hardware Abstraction Layer */
35
35
#include <hw_defs.h>
36
36
#include <hw_mmu.h>
37
37
 
38
 
#include <dspbridge/pwr_sh.h>
 
38
#include <dspbridge/pwr.h>
39
39
 
40
40
/*  ----------------------------------- Bridge Driver */
41
41
#include <dspbridge/dspdeh.h>
118
118
 
119
119
                if (!status) {
120
120
                        /* Update the Bridger Driver state */
121
 
                        dev_context->dw_brd_state = BRD_DSP_HIBERNATION;
 
121
                        dev_context->brd_state = BRD_DSP_HIBERNATION;
122
122
#ifdef CONFIG_TIDSPBRIDGE_DVFS
123
123
                        status =
124
 
                            dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
 
124
                            dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
125
125
                        if (!hio_mgr) {
126
126
                                status = DSP_EHANDLE;
127
127
                                return status;
163
163
        if ((dw_cmd != PWR_DEEPSLEEP) && (dw_cmd != PWR_EMERGENCYDEEPSLEEP))
164
164
                return -EINVAL;
165
165
 
166
 
        switch (dev_context->dw_brd_state) {
 
166
        switch (dev_context->brd_state) {
167
167
        case BRD_RUNNING:
168
168
                omap_mbox_save_ctx(dev_context->mbox);
169
169
                if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
216
216
                pr_err("%s: Timed out waiting for DSP off mode, state %x\n",
217
217
                       __func__, pwr_state);
218
218
#ifdef CONFIG_TIDSPBRIDGE_NTFY_PWRERR
219
 
                dev_get_deh_mgr(dev_context->hdev_obj, &hdeh_mgr);
 
219
                dev_get_deh_mgr(dev_context->dev_obj, &hdeh_mgr);
220
220
                bridge_deh_notify(hdeh_mgr, DSP_PWRERROR, 0);
221
221
#endif /* CONFIG_TIDSPBRIDGE_NTFY_PWRERR */
222
222
                return -ETIMEDOUT;
223
223
        } else {
224
224
                /* Update the Bridger Driver state */
225
225
                if (dsp_test_sleepstate == PWRDM_POWER_OFF)
226
 
                        dev_context->dw_brd_state = BRD_HIBERNATION;
 
226
                        dev_context->brd_state = BRD_HIBERNATION;
227
227
                else
228
 
                        dev_context->dw_brd_state = BRD_RETENTION;
 
228
                        dev_context->brd_state = BRD_RETENTION;
229
229
 
230
230
                /* Disable wdt on hibernation. */
231
231
                dsp_wdt_enable(false);
258
258
#ifdef CONFIG_PM
259
259
 
260
260
        /* Check the board state, if it is not 'SLEEP' then return */
261
 
        if (dev_context->dw_brd_state == BRD_RUNNING ||
262
 
            dev_context->dw_brd_state == BRD_STOPPED) {
 
261
        if (dev_context->brd_state == BRD_RUNNING ||
 
262
            dev_context->brd_state == BRD_STOPPED) {
263
263
                /* The Device is in 'RET' or 'OFF' state and Bridge state is not
264
264
                 * 'SLEEP', this means state inconsistency, so return */
265
265
                return 0;
269
269
        sm_interrupt_dsp(dev_context, MBX_PM_DSPWAKEUP);
270
270
 
271
271
        /* Set the device state to RUNNIG */
272
 
        dev_context->dw_brd_state = BRD_RUNNING;
 
272
        dev_context->brd_state = BRD_RUNNING;
273
273
#endif /* CONFIG_PM */
274
274
        return status;
275
275
}
351
351
 
352
352
        dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
353
353
                __func__, voltage_domain, level);
354
 
        if ((dev_context->dw_brd_state == BRD_HIBERNATION) ||
355
 
            (dev_context->dw_brd_state == BRD_RETENTION) ||
356
 
            (dev_context->dw_brd_state == BRD_DSP_HIBERNATION)) {
 
354
        if ((dev_context->brd_state == BRD_HIBERNATION) ||
 
355
            (dev_context->brd_state == BRD_RETENTION) ||
 
356
            (dev_context->brd_state == BRD_DSP_HIBERNATION)) {
357
357
                dev_dbg(bridge, "OPP: %s IVA in sleep. No message to DSP\n");
358
358
                return 0;
359
 
        } else if ((dev_context->dw_brd_state == BRD_RUNNING)) {
 
359
        } else if ((dev_context->brd_state == BRD_RUNNING)) {
360
360
                /* Send a prenotificatio to DSP */
361
361
                dev_dbg(bridge, "OPP: %s sent notification to DSP\n", __func__);
362
362
                sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_PRENOTIFY);
382
382
        u32 voltage_domain;
383
383
        struct io_mgr *hio_mgr;
384
384
 
385
 
        status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
 
385
        status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
386
386
        if (!hio_mgr)
387
387
                return -EFAULT;
388
388
 
390
390
        level = *((u32 *) pargs + 1);
391
391
        dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
392
392
                __func__, voltage_domain, level);
393
 
        if ((dev_context->dw_brd_state == BRD_HIBERNATION) ||
394
 
            (dev_context->dw_brd_state == BRD_RETENTION) ||
395
 
            (dev_context->dw_brd_state == BRD_DSP_HIBERNATION)) {
 
393
        if ((dev_context->brd_state == BRD_HIBERNATION) ||
 
394
            (dev_context->brd_state == BRD_RETENTION) ||
 
395
            (dev_context->brd_state == BRD_DSP_HIBERNATION)) {
396
396
                /* Update the OPP value in shared memory */
397
397
                io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
398
398
                dev_dbg(bridge, "OPP: %s IVA in sleep. Wrote to shm\n",
399
399
                        __func__);
400
 
        } else if ((dev_context->dw_brd_state == BRD_RUNNING)) {
 
400
        } else if ((dev_context->brd_state == BRD_RUNNING)) {
401
401
                /* Update the OPP value in shared memory */
402
402
                io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
403
403
                /* Send a post notification to DSP */
434
434
 
435
435
        switch (clock_id) {
436
436
        case BPWR_GP_TIMER5:
437
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
438
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
437
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
438
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
439
439
                if (enable) {
440
440
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
441
441
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
443
443
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
444
444
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
445
445
                }
446
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
447
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
446
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
447
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
448
448
                break;
449
449
        case BPWR_GP_TIMER6:
450
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
451
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
450
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
451
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
452
452
                if (enable) {
453
453
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
454
454
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
456
456
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
457
457
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
458
458
                }
459
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
460
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
459
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
460
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
461
461
                break;
462
462
        case BPWR_GP_TIMER7:
463
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
464
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
463
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
464
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
465
465
                if (enable) {
466
466
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
467
467
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
469
469
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
470
470
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
471
471
                }
472
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
473
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
472
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
473
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
474
474
                break;
475
475
        case BPWR_GP_TIMER8:
476
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
477
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
476
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
477
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
478
478
                if (enable) {
479
479
                        iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
480
480
                        mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
482
482
                        mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
483
483
                        iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
484
484
                }
485
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
486
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
485
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
486
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
487
487
                break;
488
488
        case BPWR_MCBSP1:
489
 
                iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8);
490
 
                mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4);
 
489
                iva2_grpsel = readl(resources->core_pm_base + 0xA8);
 
490
                mpu_grpsel = readl(resources->core_pm_base + 0xA4);
491
491
                if (enable) {
492
492
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
493
493
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
495
495
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
496
496
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
497
497
                }
498
 
                writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8);
499
 
                writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4);
 
498
                writel(iva2_grpsel, resources->core_pm_base + 0xA8);
 
499
                writel(mpu_grpsel, resources->core_pm_base + 0xA4);
500
500
                break;
501
501
        case BPWR_MCBSP2:
502
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
503
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
502
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
503
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
504
504
                if (enable) {
505
505
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
506
506
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
508
508
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
509
509
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
510
510
                }
511
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
512
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
511
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
512
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
513
513
                break;
514
514
        case BPWR_MCBSP3:
515
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
516
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
515
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
516
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
517
517
                if (enable) {
518
518
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
519
519
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
521
521
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
522
522
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
523
523
                }
524
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
525
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
524
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
525
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
526
526
                break;
527
527
        case BPWR_MCBSP4:
528
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
529
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
528
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
529
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
530
530
                if (enable) {
531
531
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
532
532
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
534
534
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
535
535
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
536
536
                }
537
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
538
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
537
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
538
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
539
539
                break;
540
540
        case BPWR_MCBSP5:
541
 
                iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
542
 
                mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
 
541
                iva2_grpsel = readl(resources->per_pm_base + 0xA8);
 
542
                mpu_grpsel = readl(resources->per_pm_base + 0xA4);
543
543
                if (enable) {
544
544
                        iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
545
545
                        mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
547
547
                        mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
548
548
                        iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
549
549
                }
550
 
                writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
551
 
                writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
 
550
                writel(iva2_grpsel, resources->per_pm_base + 0xA8);
 
551
                writel(mpu_grpsel, resources->per_pm_base + 0xA4);
552
552
                break;
553
553
        }
554
554
}