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Viewing changes to arch/powerpc/kernel/entry_64.S

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/powerpc/kernel/entry_64.S
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        std     r24,THREAD_VRSAVE(r3)
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif /* CONFIG_ALTIVEC */
 
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#ifdef CONFIG_PPC64
 
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BEGIN_FTR_SECTION
 
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        mfspr   r25,SPRN_DSCR
 
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        std     r25,THREAD_DSCR(r3)
 
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END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 
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#endif
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        and.    r0,r0,r22
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        beq+    1f
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        andc    r22,r22,r0
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  FTR_SECTION_ELSE_NESTED(95)
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        clrrdi  r6,r8,40        /* get its 1T ESID */
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        clrrdi  r9,r1,40        /* get current sp 1T ESID */
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  ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
 
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  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
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FTR_SECTION_ELSE
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        b       2f
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
 
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
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        clrldi. r0,r6,2         /* is new ESID c00000000? */
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        cmpd    cr1,r6,r9       /* or is new ESID the same as current ESID? */
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        cror    eq,4*cr1+eq,eq
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        li      r9,MMU_SEGSIZE_1T       /* insert B field */
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        oris    r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
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        rldimi  r7,r9,SLB_VSID_SSIZE_SHIFT,0
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END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
 
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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        /* Update the last bolted SLB.  No write barriers are needed
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         * here, provided we only update the current CPU's SLB shadow
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        std     r7,SLBSHADOW_STACKVSID(r9)  /* Save VSID */
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        std     r0,SLBSHADOW_STACKESID(r9)  /* Save ESID */
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        /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
 
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        /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
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         * we have 1TB segments, the only CPUs known to have the errata
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         * only support less than 1TB of system memory and we'll never
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         * actually hit this code path.
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        mtspr   SPRN_VRSAVE,r0          /* if G4, restore VRSAVE reg */
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif /* CONFIG_ALTIVEC */
 
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#ifdef CONFIG_PPC64
 
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BEGIN_FTR_SECTION
 
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        ld      r0,THREAD_DSCR(r4)
 
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        cmpd    r0,r25
 
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        beq     1f
 
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        mtspr   SPRN_DSCR,r0
 
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1:      
 
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END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 
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#endif
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        /* r3-r13 are destroyed -- Cort */
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        REST_8GPRS(14, r1)
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_STATIC(rtas_return_loc)
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        /* relocation is off at this point */
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        mfspr   r4,SPRN_SPRG_PACA       /* Get PACA */
 
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        GET_PACA(r4)
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        clrldi  r4,r4,2                 /* convert to realmode address */
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        bcl     20,31,$+4
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        REST_8GPRS(14, r1)              /* Restore the non-volatiles */
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        REST_10GPRS(22, r1)             /* ditto */
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        mfspr   r13,SPRN_SPRG_PACA
 
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        GET_PACA(r13)
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        ld      r4,_CCR(r1)
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        mtcr    r4