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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <plat/mailbox.h>
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#include <mach/irqs.h>
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#define MAILBOX_REVISION 0x000
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#define MAILBOX_SYSCONFIG 0x010
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#define MAILBOX_SYSSTATUS 0x014
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#define MAILBOX_MESSAGE(m) (0x040 + 0x4 * (m))
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#define MAILBOX_FIFOSTATUS(m) (0x080 + 0x4 * (m))
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#define MAILBOX_MSGSTATUS(m) (0x0c0 + 0x4 * (m))
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#define MAILBOX_IRQSTATUS(u) (0x100 + 0x8 * (u))
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#define MAILBOX_IRQENABLE(u) (0x104 + 0x8 * (u))
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#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
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#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
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#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
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#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
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#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
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#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
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#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
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#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
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#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
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#define MBOX_REG_SIZE 0x120
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#define MBOX_NUM_USER 2
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#define OMAP4_MBOX_NUM_USER 3
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#define OMAP4_MBOX_REG_SIZE 0x130
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#define MBOX_NR_REGS 2
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#define OMAP4_MBOX_NR_REGS 3
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/* SYSCONFIG: register bit definition */
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#define AUTOIDLE (1 << 0)
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#define SOFTRESET (1 << 1)
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#define SMARTIDLE (2 << 3)
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#define OMAP4_SOFTRESET (1 << 0)
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#define OMAP4_NOIDLE (1 << 2)
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#define OMAP4_SMARTIDLE (2 << 2)
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#define RESETDONE (1 << 0)
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#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
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#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
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static void __iomem *mbox_base;
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static int nr_mbox_users;
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static struct clk *mbox_ick_handle;
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struct omap_mbox2_fifo {
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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unsigned long timeout;
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pm_runtime_enable(mbox->dev->parent);
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pm_runtime_get_sync(mbox->dev->parent);
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if (!cpu_is_omap44xx()) {
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mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
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if (IS_ERR(mbox_ick_handle)) {
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printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
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PTR_ERR(mbox_ick_handle));
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return PTR_ERR(mbox_ick_handle);
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clk_enable(mbox_ick_handle);
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if (cpu_is_omap44xx()) {
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mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
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timeout = jiffies + msecs_to_jiffies(20);
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l = mbox_read_reg(MAILBOX_SYSCONFIG);
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if (!(l & OMAP4_SOFTRESET))
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} while (!time_after(jiffies, timeout));
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if (l & OMAP4_SOFTRESET) {
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pr_err("Can't take mailbox out of reset\n");
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mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
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timeout = jiffies + msecs_to_jiffies(20);
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l = mbox_read_reg(MAILBOX_SYSSTATUS);
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} while (!time_after(jiffies, timeout));
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if (!(l & RESETDONE)) {
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pr_err("Can't take mailbox out of reset\n");
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l = mbox_read_reg(MAILBOX_REVISION);
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pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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omap2_mbox_enable_irq(mbox, IRQ_RX);
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pm_runtime_put_sync(mbox->dev->parent);
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pm_runtime_disable(mbox->dev->parent);
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if (!cpu_is_omap44xx()) {
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clk_disable(mbox_ick_handle);
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clk_put(mbox_ick_handle);
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mbox_ick_handle = NULL;
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/* Mailbox FIFO handle functions */
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static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
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/* Save irqs per user */
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for (j = 0, i = 0; j < nr_mbox_users; i++, j++) {
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if (cpu_is_omap44xx())
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mbox_ctx[i] = mbox_read_reg(OMAP4_MAILBOX_IRQENABLE(j));
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mbox_ctx[i] = mbox_read_reg(MAILBOX_IRQENABLE(j));
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struct omap_mbox2_priv *p = mbox->priv;
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if (cpu_is_omap44xx())
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nr_regs = OMAP4_MBOX_NR_REGS;
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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p->ctx[i] = mbox_read_reg(i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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omap2_mbox_shutdown(mbox);
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static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
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omap2_mbox_startup(mbox);
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/* Restore irqs per user */
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for (j = 0, i = 0; j < nr_mbox_users; i++, j++) {
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if (cpu_is_omap44xx())
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mbox_write_reg(mbox_ctx[i], OMAP4_MAILBOX_IRQENABLE(j));
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mbox_write_reg(mbox_ctx[i], MAILBOX_IRQENABLE(j));
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struct omap_mbox2_priv *p = mbox->priv;
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if (cpu_is_omap44xx())
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nr_regs = OMAP4_MBOX_NR_REGS;
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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mbox_write_reg(p->ctx[i], i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,