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Viewing changes to arch/blackfin/mach-bf561/secondary.S

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/blackfin/mach-bf561/secondary.S
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#include <asm/asm-offsets.h>
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#include <asm/trace.h>
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__INIT
 
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/*
 
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 * This code must come first as CoreB is hardcoded (in hardware)
 
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 * to start at the beginning of its L1 instruction memory.
 
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 */
 
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.section .l1.text.head
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/* Lay the initial stack into the L1 scratch area of Core B */
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#define INITIAL_STACK   (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
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.LWAIT_HERE:
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        jump .LWAIT_HERE;
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ENDPROC(_coreb_trampoline_start)
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ENTRY(_coreb_trampoline_end)
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#ifdef CONFIG_HOTPLUG_CPU
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.section ".text"
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ENTRY(_set_sicb_iwr)
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        P0.H = hi(SICB_IWR0);
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        P0.L = lo(SICB_IWR0);
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        P1.H = hi(SICB_IWR1);
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        P1.L = lo(SICB_IWR1);
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        [P0] = R0;
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        [P1] = R1;
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        SSYNC;
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        RTS;
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ENDPROC(_set_sicb_iwr)
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ENTRY(_coreb_sleep)
 
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ENTRY(_coreb_die)
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        sp.l = lo(INITIAL_STACK);
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        sp.h = hi(INITIAL_STACK);
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        fp = sp;
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        usp = sp;
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        call _set_sicb_iwr;
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        CLI R2;
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        SSYNC;
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        IDLE;
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        STI R2;
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        R0 = IWR_DISABLE_ALL;
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        R1 = IWR_DISABLE_ALL;
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        call _set_sicb_iwr;
 
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        P0.H = hi(SYSMMR_BASE);
 
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        P0.L = lo(SYSMMR_BASE);
 
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        [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
 
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        [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
 
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        SSYNC;
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        p0.h = hi(COREB_L1_CODE_START);
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        p0.l = lo(COREB_L1_CODE_START);
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        jump (p0);
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ENDPROC(_coreb_sleep)
 
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ENDPROC(_coreb_die)
 
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#endif
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__CPUINIT
 
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__INIT
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ENTRY(_coreb_start)
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        [--sp] = reti;
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