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Viewing changes to drivers/net/stmmac/dwmac_lib.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/net/stmmac/dwmac_lib.c
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#undef DWMAC_DMA_DEBUG
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#ifdef DWMAC_DMA_DEBUG
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#define DBG(fmt, args...)  printk(fmt, ## args)
 
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#define DWMAC_LIB_DBG(fmt, args...)  printk(fmt, ## args)
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#else
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#define DBG(fmt, args...)  do { } while (0)
 
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#define DWMAC_LIB_DBG(fmt, args...)  do { } while (0)
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#endif
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/* CSR1 enables the transmit DMA to check for new descriptor */
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        /* read the status register (CSR5) */
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        u32 intr_status = readl(ioaddr + DMA_STATUS);
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        DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
 
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        DWMAC_LIB_DBG(KERN_INFO "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
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#ifdef DWMAC_DMA_DEBUG
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        /* It displays the DMA process states (CSR5 register) */
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        show_tx_process_state(intr_status);
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#endif
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        /* ABNORMAL interrupts */
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        if (unlikely(intr_status & DMA_STATUS_AIS)) {
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                DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
 
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                DWMAC_LIB_DBG(KERN_INFO "CSR5[15] DMA ABNORMAL IRQ: ");
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                if (unlikely(intr_status & DMA_STATUS_UNF)) {
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                        DBG(INFO, "transmit underflow\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "transmit underflow\n");
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                        ret = tx_hard_error_bump_tc;
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                        x->tx_undeflow_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_TJT)) {
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                        DBG(INFO, "transmit jabber\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "transmit jabber\n");
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                        x->tx_jabber_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_OVF)) {
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                        DBG(INFO, "recv overflow\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "recv overflow\n");
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                        x->rx_overflow_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_RU)) {
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                        DBG(INFO, "receive buffer unavailable\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "receive buffer unavailable\n");
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                        x->rx_buf_unav_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_RPS)) {
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                        DBG(INFO, "receive process stopped\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "receive process stopped\n");
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                        x->rx_process_stopped_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_RWT)) {
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                        DBG(INFO, "receive watchdog\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "receive watchdog\n");
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                        x->rx_watchdog_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_ETI)) {
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                        DBG(INFO, "transmit early interrupt\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "transmit early interrupt\n");
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                        x->tx_early_irq++;
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                }
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                if (unlikely(intr_status & DMA_STATUS_TPS)) {
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                        DBG(INFO, "transmit process stopped\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "transmit process stopped\n");
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                        x->tx_process_stopped_irq++;
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                        ret = tx_hard_error;
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                }
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                if (unlikely(intr_status & DMA_STATUS_FBI)) {
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                        DBG(INFO, "fatal bus error\n");
 
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                        DWMAC_LIB_DBG(KERN_INFO "fatal bus error\n");
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                        x->fatal_bus_error_irq++;
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                        ret = tx_hard_error;
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                }
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        /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
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        writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
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        DBG(INFO, "\n\n");
 
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        DWMAC_LIB_DBG(KERN_INFO "\n\n");
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        return ret;
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}
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