2
* Copyright (c) 2010 Broadcom Corporation
4
* Permission to use, copy, modify, and/or distribute this software for any
5
* purpose with or without fee is hereby granted, provided that the above
6
* copyright notice and this permission notice appear in all copies.
8
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16
#include <linux/delay.h>
17
#include <linux/kernel.h>
18
#include <linux/string.h>
19
#include <linux/module.h>
20
#include <linux/pci.h>
22
#include <linux/netdevice.h>
32
#include "siutils_priv.h"
34
#define PMU_ERROR(args)
37
#define PMU_MSG(args) printf args
42
/* To check in verbose debugging messages not intended
43
* to be on except on private builds.
45
#define PMU_NONE(args)
47
/* PLL controls/clocks */
48
static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
50
static u32 si_pmu1_cpuclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc);
51
static u32 si_pmu1_alpclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc);
54
static bool si_pmu_res_depfltr_bb(si_t *sih);
55
static bool si_pmu_res_depfltr_ncb(si_t *sih);
56
static bool si_pmu_res_depfltr_paldo(si_t *sih);
57
static bool si_pmu_res_depfltr_npaldo(si_t *sih);
58
static u32 si_pmu_res_deps(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
60
static uint si_pmu_res_uptime(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
62
static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
63
static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
64
struct osl_info *osh, u8 spuravoid);
66
static void si_pmu_set_4330_plldivs(si_t *sih);
69
#define FVCO_880 880000 /* 880MHz */
70
#define FVCO_1760 1760000 /* 1760MHz */
71
#define FVCO_1440 1440000 /* 1440MHz */
72
#define FVCO_960 960000 /* 960MHz */
74
/* Read/write a chipcontrol reg */
75
u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
77
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
79
return si_corereg(sih, SI_CC_IDX,
80
offsetof(chipcregs_t, chipcontrol_data), mask, val);
83
/* Read/write a regcontrol reg */
84
u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
86
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
88
return si_corereg(sih, SI_CC_IDX,
89
offsetof(chipcregs_t, regcontrol_data), mask, val);
92
/* Read/write a pllcontrol reg */
93
u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
95
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
97
return si_corereg(sih, SI_CC_IDX,
98
offsetof(chipcregs_t, pllcontrol_data), mask, val);
102
void si_pmu_pllupd(si_t *sih)
104
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
105
PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
108
/* Setup switcher voltage */
109
void si_pmu_set_switcher_voltage(si_t *sih, struct osl_info *osh, u8 bb_voltage,
115
ASSERT(sih->cccaps & CC_CAP_PMU);
117
/* Remember original core before switch to chipc */
118
origidx = si_coreidx(sih);
119
cc = si_setcoreidx(sih, SI_CC_IDX);
122
W_REG(osh, &cc->regcontrol_addr, 0x01);
123
W_REG(osh, &cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
125
W_REG(osh, &cc->regcontrol_addr, 0x00);
126
W_REG(osh, &cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14);
128
/* Return to original core */
129
si_setcoreidx(sih, origidx);
132
void si_pmu_set_ldo_voltage(si_t *sih, struct osl_info *osh, u8 ldo, u8 voltage)
134
u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
137
ASSERT(sih->cccaps & CC_CAP_PMU);
140
case BCM4336_CHIP_ID:
142
case SET_LDO_VOLTAGE_CLDO_PWM:
147
case SET_LDO_VOLTAGE_CLDO_BURST:
152
case SET_LDO_VOLTAGE_LNLDO1:
162
case BCM4330_CHIP_ID:
164
case SET_LDO_VOLTAGE_CBUCK_PWM:
179
shift = sr_cntl_shift + rc_shift;
181
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
183
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
184
mask << shift, (voltage & mask) << shift);
187
/* d11 slow to fast clock transition time in slow clock cycles */
188
#define D11SCC_SLOW2FAST_TRANSITION 2
190
u16 si_pmu_fast_pwrup_delay(si_t *sih, struct osl_info *osh)
192
uint delay = PMU_MAX_TRANSITION_DLY;
197
chn[0] = 0; /* to suppress compile error */
200
ASSERT(sih->cccaps & CC_CAP_PMU);
202
/* Remember original core before switch to chipc */
203
origidx = si_coreidx(sih);
204
cc = si_setcoreidx(sih, SI_CC_IDX);
208
case BCM43224_CHIP_ID:
209
case BCM43225_CHIP_ID:
210
case BCM43421_CHIP_ID:
211
case BCM43235_CHIP_ID:
212
case BCM43236_CHIP_ID:
213
case BCM43238_CHIP_ID:
214
case BCM4331_CHIP_ID:
215
case BCM6362_CHIP_ID:
216
case BCM4313_CHIP_ID:
217
delay = ISSIM_ENAB(sih) ? 70 : 3700;
219
case BCM4329_CHIP_ID:
223
u32 ilp = si_ilp_clock(sih);
225
(si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
226
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
228
delay = (11 * delay) / 10;
231
case BCM4319_CHIP_ID:
232
delay = ISSIM_ENAB(sih) ? 70 : 3700;
234
case BCM4336_CHIP_ID:
238
u32 ilp = si_ilp_clock(sih);
240
(si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
241
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
243
delay = (11 * delay) / 10;
246
case BCM4330_CHIP_ID:
250
u32 ilp = si_ilp_clock(sih);
252
(si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
253
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
255
delay = (11 * delay) / 10;
261
/* Return to original core */
262
si_setcoreidx(sih, origidx);
267
u32 si_pmu_force_ilp(si_t *sih, struct osl_info *osh, bool force)
273
ASSERT(sih->cccaps & CC_CAP_PMU);
275
/* Remember original core before switch to chipc */
276
origidx = si_coreidx(sih);
277
cc = si_setcoreidx(sih, SI_CC_IDX);
280
oldpmucontrol = R_REG(osh, &cc->pmucontrol);
282
W_REG(osh, &cc->pmucontrol, oldpmucontrol &
283
~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
285
W_REG(osh, &cc->pmucontrol, oldpmucontrol |
286
(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
288
/* Return to original core */
289
si_setcoreidx(sih, origidx);
291
return oldpmucontrol;
294
/* Setup resource up/down timers */
300
/* Change resource dependancies masks */
302
u32 res_mask; /* resources (chip specific) */
303
s8 action; /* action */
304
u32 depend_mask; /* changes to the dependancies mask */
305
bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return true */
308
/* Resource dependancies mask change action */
309
#define RES_DEPEND_SET 0 /* Override the dependancies mask */
310
#define RES_DEPEND_ADD 1 /* Add to the dependancies mask */
311
#define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */
313
static const pmu_res_updown_t bcm4328a0_res_updown[] = {
315
RES4328_EXT_SWITCHER_PWM, 0x0101}, {
316
RES4328_BB_SWITCHER_PWM, 0x1f01}, {
317
RES4328_BB_SWITCHER_BURST, 0x010f}, {
318
RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
319
RES4328_ILP_REQUEST, 0x0202}, {
320
RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
321
RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
322
RES4328_ROM_SWITCH, 0x0101}, {
323
RES4328_PA_REF_LDO, 0x0f01}, {
324
RES4328_RADIO_LDO, 0x0f01}, {
325
RES4328_AFE_LDO, 0x0f01}, {
326
RES4328_PLL_LDO, 0x0f01}, {
327
RES4328_BG_FILTBYP, 0x0101}, {
328
RES4328_TX_FILTBYP, 0x0101}, {
329
RES4328_RX_FILTBYP, 0x0101}, {
330
RES4328_XTAL_PU, 0x0101}, {
331
RES4328_XTAL_EN, 0xa001}, {
332
RES4328_BB_PLL_FILTBYP, 0x0101}, {
333
RES4328_RF_PLL_FILTBYP, 0x0101}, {
334
RES4328_BB_PLL_PU, 0x0701}
337
static const pmu_res_depend_t bcm4328a0_res_depend[] = {
338
/* Adjust ILP request resource not to force ext/BB switchers into burst mode */
340
PMURES_BIT(RES4328_ILP_REQUEST),
342
PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
343
PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
346
static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
348
RES4325_HT_AVAIL, 0x0300}, {
349
RES4325_BBPLL_PWRSW_PU, 0x0101}, {
350
RES4325_RFPLL_PWRSW_PU, 0x0101}, {
351
RES4325_ALP_AVAIL, 0x0100}, {
352
RES4325_XTAL_PU, 0x1000}, {
353
RES4325_LNLDO1_PU, 0x0800}, {
354
RES4325_CLDO_CBUCK_PWM, 0x0101}, {
355
RES4325_CBUCK_PWM, 0x0803}
358
static const pmu_res_updown_t bcm4325a0_res_updown[] = {
360
RES4325_XTAL_PU, 0x1501}
363
static const pmu_res_depend_t bcm4325a0_res_depend[] = {
364
/* Adjust OTP PU resource dependencies - remove BB BURST */
366
PMURES_BIT(RES4325_OTP_PU),
368
PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
369
/* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
371
PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
373
PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
374
PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
375
/* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
377
PMURES_BIT(RES4325_HT_AVAIL),
379
PMURES_BIT(RES4325_RX_PWRSW_PU) |
380
PMURES_BIT(RES4325_TX_PWRSW_PU) |
381
PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
382
PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
383
/* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
385
PMURES_BIT(RES4325_ILP_REQUEST) |
386
PMURES_BIT(RES4325_ABUCK_BURST) |
387
PMURES_BIT(RES4325_ABUCK_PWM) |
388
PMURES_BIT(RES4325_LNLDO1_PU) |
389
PMURES_BIT(RES4325C1_LNLDO2_PU) |
390
PMURES_BIT(RES4325_XTAL_PU) |
391
PMURES_BIT(RES4325_ALP_AVAIL) |
392
PMURES_BIT(RES4325_RX_PWRSW_PU) |
393
PMURES_BIT(RES4325_TX_PWRSW_PU) |
394
PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
395
PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
396
PMURES_BIT(RES4325_AFE_PWRSW_PU) |
397
PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
398
PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
399
PMURES_BIT(RES4325B0_CBUCK_LPOM) |
400
PMURES_BIT(RES4325B0_CBUCK_BURST) |
401
PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
404
static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
406
RES4315_HT_AVAIL, 0x0101}, {
407
RES4315_XTAL_PU, 0x0100}, {
408
RES4315_LNLDO1_PU, 0x0100}, {
409
RES4315_PALDO_PU, 0x0100}, {
410
RES4315_CLDO_PU, 0x0100}, {
411
RES4315_CBUCK_PWM, 0x0100}, {
412
RES4315_CBUCK_BURST, 0x0100}, {
413
RES4315_CBUCK_LPOM, 0x0100}
416
static const pmu_res_updown_t bcm4315a0_res_updown[] = {
418
RES4315_XTAL_PU, 0x2501}
421
static const pmu_res_depend_t bcm4315a0_res_depend[] = {
422
/* Adjust OTP PU resource dependencies - not need PALDO unless write */
424
PMURES_BIT(RES4315_OTP_PU),
426
PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
427
/* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
429
PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
431
PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
432
/* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
434
PMURES_BIT(RES4315_HT_AVAIL),
436
PMURES_BIT(RES4315_RX_PWRSW_PU) |
437
PMURES_BIT(RES4315_TX_PWRSW_PU) |
438
PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
439
PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
440
/* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
442
PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
443
PMURES_BIT(RES4315_LNLDO1_PU) |
444
PMURES_BIT(RES4315_OTP_PU) |
445
PMURES_BIT(RES4315_LNLDO2_PU) |
446
PMURES_BIT(RES4315_XTAL_PU) |
447
PMURES_BIT(RES4315_ALP_AVAIL) |
448
PMURES_BIT(RES4315_RX_PWRSW_PU) |
449
PMURES_BIT(RES4315_TX_PWRSW_PU) |
450
PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
451
PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
452
PMURES_BIT(RES4315_AFE_PWRSW_PU) |
453
PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
454
PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
455
PMURES_BIT(RES4315_CBUCK_LPOM) |
456
PMURES_BIT(RES4315_CBUCK_BURST) |
457
PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
460
/* 4329 specific. needs to come back this issue later */
461
static const pmu_res_updown_t bcm4329_res_updown[] = {
463
RES4329_XTAL_PU, 0x1501}
466
static const pmu_res_depend_t bcm4329_res_depend[] = {
467
/* Adjust HT Avail resource dependencies */
469
PMURES_BIT(RES4329_HT_AVAIL),
471
PMURES_BIT(RES4329_CBUCK_LPOM) |
472
PMURES_BIT(RES4329_CBUCK_BURST) |
473
PMURES_BIT(RES4329_CBUCK_PWM) |
474
PMURES_BIT(RES4329_CLDO_PU) |
475
PMURES_BIT(RES4329_PALDO_PU) |
476
PMURES_BIT(RES4329_LNLDO1_PU) |
477
PMURES_BIT(RES4329_XTAL_PU) |
478
PMURES_BIT(RES4329_ALP_AVAIL) |
479
PMURES_BIT(RES4329_RX_PWRSW_PU) |
480
PMURES_BIT(RES4329_TX_PWRSW_PU) |
481
PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
482
PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
483
PMURES_BIT(RES4329_AFE_PWRSW_PU) |
484
PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
487
static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
489
RES4319_HT_AVAIL, 0x0101}, {
490
RES4319_XTAL_PU, 0x0100}, {
491
RES4319_LNLDO1_PU, 0x0100}, {
492
RES4319_PALDO_PU, 0x0100}, {
493
RES4319_CLDO_PU, 0x0100}, {
494
RES4319_CBUCK_PWM, 0x0100}, {
495
RES4319_CBUCK_BURST, 0x0100}, {
496
RES4319_CBUCK_LPOM, 0x0100}
499
static const pmu_res_updown_t bcm4319a0_res_updown[] = {
501
RES4319_XTAL_PU, 0x3f01}
504
static const pmu_res_depend_t bcm4319a0_res_depend[] = {
505
/* Adjust OTP PU resource dependencies - not need PALDO unless write */
507
PMURES_BIT(RES4319_OTP_PU),
509
PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
510
/* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
512
PMURES_BIT(RES4319_HT_AVAIL),
514
PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
515
/* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
517
PMURES_BIT(RES4319_HT_AVAIL),
519
PMURES_BIT(RES4319_RX_PWRSW_PU) |
520
PMURES_BIT(RES4319_TX_PWRSW_PU) |
521
PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
522
PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
523
PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
526
static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
528
RES4336_HT_AVAIL, 0x0101}, {
529
RES4336_XTAL_PU, 0x0100}, {
530
RES4336_CLDO_PU, 0x0100}, {
531
RES4336_CBUCK_PWM, 0x0100}, {
532
RES4336_CBUCK_BURST, 0x0100}, {
533
RES4336_CBUCK_LPOM, 0x0100}
536
static const pmu_res_updown_t bcm4336a0_res_updown[] = {
538
RES4336_HT_AVAIL, 0x0D01}
541
static const pmu_res_depend_t bcm4336a0_res_depend[] = {
542
/* Just a dummy entry for now */
544
PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
547
static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
549
RES4330_HT_AVAIL, 0x0101}, {
550
RES4330_XTAL_PU, 0x0100}, {
551
RES4330_CLDO_PU, 0x0100}, {
552
RES4330_CBUCK_PWM, 0x0100}, {
553
RES4330_CBUCK_BURST, 0x0100}, {
554
RES4330_CBUCK_LPOM, 0x0100}
557
static const pmu_res_updown_t bcm4330a0_res_updown[] = {
559
RES4330_HT_AVAIL, 0x0e02}
562
static const pmu_res_depend_t bcm4330a0_res_depend[] = {
563
/* Just a dummy entry for now */
565
PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
568
/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
569
static bool si_pmu_res_depfltr_bb(si_t *sih)
571
return (sih->boardflags & BFL_BUCKBOOST) != 0;
574
/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
575
static bool si_pmu_res_depfltr_ncb(si_t *sih)
578
return (sih->boardflags & BFL_NOCBUCK) != 0;
581
/* true if the power topology uses the PALDO */
582
static bool si_pmu_res_depfltr_paldo(si_t *sih)
584
return (sih->boardflags & BFL_PALDO) != 0;
587
/* true if the power topology doesn't use the PALDO */
588
static bool si_pmu_res_depfltr_npaldo(si_t *sih)
590
return (sih->boardflags & BFL_PALDO) == 0;
593
#define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \
594
sih->boardtype == BCM94325BGABU_BOARD)
596
/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
597
static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
599
u32 min_mask = 0, max_mask = 0;
604
rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
606
/* determine min/max rsrc masks */
608
case BCM43224_CHIP_ID:
609
case BCM43225_CHIP_ID:
610
case BCM43421_CHIP_ID:
611
case BCM43235_CHIP_ID:
612
case BCM43236_CHIP_ID:
613
case BCM43238_CHIP_ID:
614
case BCM4331_CHIP_ID:
615
case BCM6362_CHIP_ID:
619
case BCM4329_CHIP_ID:
620
/* 4329 spedific issue. Needs to come back this issue later */
621
/* Down to save the power. */
623
PMURES_BIT(RES4329_CBUCK_LPOM) |
624
PMURES_BIT(RES4329_CLDO_PU);
625
/* Allow (but don't require) PLL to turn on */
628
case BCM4319_CHIP_ID:
629
/* We only need a few resources to be kept on all the time */
630
min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
631
PMURES_BIT(RES4319_CLDO_PU);
633
/* Allow everything else to be turned on upon requests */
634
max_mask = ~(~0 << rsrcs);
636
case BCM4336_CHIP_ID:
637
/* Down to save the power. */
639
PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
640
| PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
641
| PMURES_BIT(RES4336_DIS_INT_RESET_PD);
642
/* Allow (but don't require) PLL to turn on */
643
max_mask = 0x1ffffff;
646
case BCM4330_CHIP_ID:
647
/* Down to save the power. */
649
PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
650
| PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
651
PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
652
/* Allow (but don't require) PLL to turn on */
653
max_mask = 0xfffffff;
656
case BCM4313_CHIP_ID:
657
min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
658
PMURES_BIT(RES4313_XTAL_PU_RSRC) |
659
PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
660
PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
667
/* Apply nvram override to min mask */
668
val = getvar(NULL, "rmin");
670
PMU_MSG(("Applying rmin=%s to min_mask\n", val));
671
min_mask = (u32) simple_strtoul(val, NULL, 0);
673
/* Apply nvram override to max mask */
674
val = getvar(NULL, "rmax");
676
PMU_MSG(("Applying rmax=%s to max_mask\n", val));
677
max_mask = (u32) simple_strtoul(val, NULL, 0);
684
/* initialize PMU resources */
685
void si_pmu_res_init(si_t *sih, struct osl_info *osh)
689
const pmu_res_updown_t *pmu_res_updown_table = NULL;
690
uint pmu_res_updown_table_sz = 0;
691
const pmu_res_depend_t *pmu_res_depend_table = NULL;
692
uint pmu_res_depend_table_sz = 0;
693
u32 min_mask = 0, max_mask = 0;
697
ASSERT(sih->cccaps & CC_CAP_PMU);
699
/* Remember original core before switch to chipc */
700
origidx = si_coreidx(sih);
701
cc = si_setcoreidx(sih, SI_CC_IDX);
705
case BCM4329_CHIP_ID:
706
/* Optimize resources up/down timers */
707
if (ISSIM_ENAB(sih)) {
708
pmu_res_updown_table = NULL;
709
pmu_res_updown_table_sz = 0;
711
pmu_res_updown_table = bcm4329_res_updown;
712
pmu_res_updown_table_sz = ARRAY_SIZE(bcm4329_res_updown);
714
/* Optimize resources dependencies */
715
pmu_res_depend_table = bcm4329_res_depend;
716
pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
719
case BCM4319_CHIP_ID:
720
/* Optimize resources up/down timers */
721
if (ISSIM_ENAB(sih)) {
722
pmu_res_updown_table = bcm4319a0_res_updown_qt;
723
pmu_res_updown_table_sz =
724
ARRAY_SIZE(bcm4319a0_res_updown_qt);
726
pmu_res_updown_table = bcm4319a0_res_updown;
727
pmu_res_updown_table_sz =
728
ARRAY_SIZE(bcm4319a0_res_updown);
730
/* Optimize resources dependancies masks */
731
pmu_res_depend_table = bcm4319a0_res_depend;
732
pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
735
case BCM4336_CHIP_ID:
736
/* Optimize resources up/down timers */
737
if (ISSIM_ENAB(sih)) {
738
pmu_res_updown_table = bcm4336a0_res_updown_qt;
739
pmu_res_updown_table_sz =
740
ARRAY_SIZE(bcm4336a0_res_updown_qt);
742
pmu_res_updown_table = bcm4336a0_res_updown;
743
pmu_res_updown_table_sz =
744
ARRAY_SIZE(bcm4336a0_res_updown);
746
/* Optimize resources dependancies masks */
747
pmu_res_depend_table = bcm4336a0_res_depend;
748
pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
751
case BCM4330_CHIP_ID:
752
/* Optimize resources up/down timers */
753
if (ISSIM_ENAB(sih)) {
754
pmu_res_updown_table = bcm4330a0_res_updown_qt;
755
pmu_res_updown_table_sz =
756
ARRAY_SIZE(bcm4330a0_res_updown_qt);
758
pmu_res_updown_table = bcm4330a0_res_updown;
759
pmu_res_updown_table_sz =
760
ARRAY_SIZE(bcm4330a0_res_updown);
762
/* Optimize resources dependancies masks */
763
pmu_res_depend_table = bcm4330a0_res_depend;
764
pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
772
rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
774
/* Program up/down timers */
775
while (pmu_res_updown_table_sz--) {
776
ASSERT(pmu_res_updown_table != NULL);
777
PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n",
778
pmu_res_updown_table[pmu_res_updown_table_sz].resnum,
779
pmu_res_updown_table[pmu_res_updown_table_sz].updown));
780
W_REG(osh, &cc->res_table_sel,
781
pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
782
W_REG(osh, &cc->res_updn_timer,
783
pmu_res_updown_table[pmu_res_updown_table_sz].updown);
785
/* Apply nvram overrides to up/down timers */
786
for (i = 0; i < rsrcs; i++) {
787
snprintf(name, sizeof(name), "r%dt", i);
788
val = getvar(NULL, name);
791
PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name,
793
W_REG(osh, &cc->res_table_sel, (u32) i);
794
W_REG(osh, &cc->res_updn_timer,
795
(u32) simple_strtoul(val, NULL, 0));
798
/* Program resource dependencies table */
799
while (pmu_res_depend_table_sz--) {
800
ASSERT(pmu_res_depend_table != NULL);
801
if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
802
&& !(pmu_res_depend_table[pmu_res_depend_table_sz].
805
for (i = 0; i < rsrcs; i++) {
806
if ((pmu_res_depend_table[pmu_res_depend_table_sz].
807
res_mask & PMURES_BIT(i)) == 0)
809
W_REG(osh, &cc->res_table_sel, i);
810
switch (pmu_res_depend_table[pmu_res_depend_table_sz].
813
PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask));
814
W_REG(osh, &cc->res_dep_mask,
816
[pmu_res_depend_table_sz].depend_mask);
819
PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
820
OR_REG(osh, &cc->res_dep_mask,
822
[pmu_res_depend_table_sz].depend_mask);
824
case RES_DEPEND_REMOVE:
825
PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
826
AND_REG(osh, &cc->res_dep_mask,
827
~pmu_res_depend_table
828
[pmu_res_depend_table_sz].depend_mask);
836
/* Apply nvram overrides to dependancies masks */
837
for (i = 0; i < rsrcs; i++) {
838
snprintf(name, sizeof(name), "r%dd", i);
839
val = getvar(NULL, name);
842
PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val,
844
W_REG(osh, &cc->res_table_sel, (u32) i);
845
W_REG(osh, &cc->res_dep_mask,
846
(u32) simple_strtoul(val, NULL, 0));
849
/* Determine min/max rsrc masks */
850
si_pmu_res_masks(sih, &min_mask, &max_mask);
852
/* It is required to program max_mask first and then min_mask */
854
/* Program max resource mask */
857
PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
858
W_REG(osh, &cc->max_res_mask, max_mask);
861
/* Program min resource mask */
864
PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));
865
W_REG(osh, &cc->min_res_mask, min_mask);
868
/* Add some delay; allow resources to come up and settle. */
871
/* Return to original core */
872
si_setcoreidx(sih, origidx);
875
/* setup pll and query clock speed */
883
/* the following table is based on 880Mhz fvco */
884
static const pmu0_xtaltab0_t pmu0_xtaltab0[] = {
886
12000, 1, 73, 349525}, {
887
13000, 2, 67, 725937}, {
888
14400, 3, 61, 116508}, {
889
15360, 4, 57, 305834}, {
890
16200, 5, 54, 336579}, {
891
16800, 6, 52, 399457}, {
892
19200, 7, 45, 873813}, {
893
19800, 8, 44, 466033}, {
895
25000, 10, 70, 419430}, {
896
26000, 11, 67, 725937}, {
897
30000, 12, 58, 699050}, {
898
38400, 13, 45, 873813}, {
903
#define PMU0_XTAL0_DEFAULT 8
905
/* setup pll and query clock speed */
915
static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = {
917
12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
918
13000, 2, 1, 6, 0xb, 0x483483}, {
919
14400, 3, 1, 10, 0xa, 0x1C71C7}, {
920
15360, 4, 1, 5, 0xb, 0x755555}, {
921
16200, 5, 1, 10, 0x5, 0x6E9E06}, {
922
16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
923
19200, 7, 1, 4, 0xb, 0x755555}, {
924
19800, 8, 1, 11, 0x4, 0xA57EB}, {
925
20000, 9, 1, 11, 0x4, 0x0}, {
926
24000, 10, 3, 11, 0xa, 0x0}, {
927
25000, 11, 5, 16, 0xb, 0x0}, {
928
26000, 12, 1, 1, 0x21, 0xD89D89}, {
929
30000, 13, 3, 8, 0xb, 0x0}, {
930
37400, 14, 3, 1, 0x46, 0x969696}, {
931
38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
932
40000, 16, 1, 2, 0xb, 0}, {
936
/* the following table is based on 880Mhz fvco */
937
static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
939
12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
940
13000, 2, 1, 6, 0xb, 0x483483}, {
941
14400, 3, 1, 10, 0xa, 0x1C71C7}, {
942
15360, 4, 1, 5, 0xb, 0x755555}, {
943
16200, 5, 1, 10, 0x5, 0x6E9E06}, {
944
16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
945
19200, 7, 1, 4, 0xb, 0x755555}, {
946
19800, 8, 1, 11, 0x4, 0xA57EB}, {
947
20000, 9, 1, 11, 0x4, 0x0}, {
948
24000, 10, 3, 11, 0xa, 0x0}, {
949
25000, 11, 5, 16, 0xb, 0x0}, {
950
26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
951
30000, 13, 3, 8, 0xb, 0x0}, {
952
33600, 14, 1, 2, 0xd, 0x186186}, {
953
38400, 15, 1, 2, 0xb, 0x755555}, {
954
40000, 16, 1, 2, 0xb, 0}, {
958
#define PMU1_XTALTAB0_880_12000K 0
959
#define PMU1_XTALTAB0_880_13000K 1
960
#define PMU1_XTALTAB0_880_14400K 2
961
#define PMU1_XTALTAB0_880_15360K 3
962
#define PMU1_XTALTAB0_880_16200K 4
963
#define PMU1_XTALTAB0_880_16800K 5
964
#define PMU1_XTALTAB0_880_19200K 6
965
#define PMU1_XTALTAB0_880_19800K 7
966
#define PMU1_XTALTAB0_880_20000K 8
967
#define PMU1_XTALTAB0_880_24000K 9
968
#define PMU1_XTALTAB0_880_25000K 10
969
#define PMU1_XTALTAB0_880_26000K 11
970
#define PMU1_XTALTAB0_880_30000K 12
971
#define PMU1_XTALTAB0_880_37400K 13
972
#define PMU1_XTALTAB0_880_38400K 14
973
#define PMU1_XTALTAB0_880_40000K 15
975
/* the following table is based on 1760Mhz fvco */
976
static const pmu1_xtaltab0_t pmu1_xtaltab0_1760[] = {
978
12000, 1, 3, 44, 0x9, 0xFFFFEF}, {
979
13000, 2, 1, 12, 0xb, 0x483483}, {
980
14400, 3, 1, 20, 0xa, 0x1C71C7}, {
981
15360, 4, 1, 10, 0xb, 0x755555}, {
982
16200, 5, 1, 20, 0x5, 0x6E9E06}, {
983
16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, {
984
19200, 7, 1, 18, 0x5, 0x17B425}, {
985
19800, 8, 1, 22, 0x4, 0xA57EB}, {
986
20000, 9, 1, 22, 0x4, 0x0}, {
987
24000, 10, 3, 22, 0xa, 0x0}, {
988
25000, 11, 5, 32, 0xb, 0x0}, {
989
26000, 12, 1, 4, 0x10, 0xEC4EC4}, {
990
30000, 13, 3, 16, 0xb, 0x0}, {
991
38400, 14, 1, 10, 0x4, 0x955555}, {
992
40000, 15, 1, 4, 0xb, 0}, {
997
#define PMU1_XTALTAB0_1760_12000K 0
998
#define PMU1_XTALTAB0_1760_13000K 1
999
#define PMU1_XTALTAB0_1760_14400K 2
1000
#define PMU1_XTALTAB0_1760_15360K 3
1001
#define PMU1_XTALTAB0_1760_16200K 4
1002
#define PMU1_XTALTAB0_1760_16800K 5
1003
#define PMU1_XTALTAB0_1760_19200K 6
1004
#define PMU1_XTALTAB0_1760_19800K 7
1005
#define PMU1_XTALTAB0_1760_20000K 8
1006
#define PMU1_XTALTAB0_1760_24000K 9
1007
#define PMU1_XTALTAB0_1760_25000K 10
1008
#define PMU1_XTALTAB0_1760_26000K 11
1009
#define PMU1_XTALTAB0_1760_30000K 12
1010
#define PMU1_XTALTAB0_1760_38400K 13
1011
#define PMU1_XTALTAB0_1760_40000K 14
1013
/* the following table is based on 1440Mhz fvco */
1014
static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = {
1016
12000, 1, 1, 1, 0x78, 0x0}, {
1017
13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
1018
14400, 3, 1, 1, 0x64, 0x0}, {
1019
15360, 4, 1, 1, 0x5D, 0xC00000}, {
1020
16200, 5, 1, 1, 0x58, 0xE38E38}, {
1021
16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
1022
19200, 7, 1, 1, 0x4B, 0}, {
1023
19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
1024
20000, 9, 1, 1, 0x48, 0x0}, {
1025
25000, 10, 1, 1, 0x39, 0x999999}, {
1026
26000, 11, 1, 1, 0x37, 0x627627}, {
1027
30000, 12, 1, 1, 0x30, 0x0}, {
1028
37400, 13, 2, 1, 0x4D, 0x15E76}, {
1029
38400, 13, 2, 1, 0x4B, 0x0}, {
1030
40000, 14, 2, 1, 0x48, 0x0}, {
1031
48000, 15, 2, 1, 0x3c, 0x0}, {
1036
#define PMU1_XTALTAB0_1440_12000K 0
1037
#define PMU1_XTALTAB0_1440_13000K 1
1038
#define PMU1_XTALTAB0_1440_14400K 2
1039
#define PMU1_XTALTAB0_1440_15360K 3
1040
#define PMU1_XTALTAB0_1440_16200K 4
1041
#define PMU1_XTALTAB0_1440_16800K 5
1042
#define PMU1_XTALTAB0_1440_19200K 6
1043
#define PMU1_XTALTAB0_1440_19800K 7
1044
#define PMU1_XTALTAB0_1440_20000K 8
1045
#define PMU1_XTALTAB0_1440_25000K 9
1046
#define PMU1_XTALTAB0_1440_26000K 10
1047
#define PMU1_XTALTAB0_1440_30000K 11
1048
#define PMU1_XTALTAB0_1440_37400K 12
1049
#define PMU1_XTALTAB0_1440_38400K 13
1050
#define PMU1_XTALTAB0_1440_40000K 14
1051
#define PMU1_XTALTAB0_1440_48000K 15
1053
#define XTAL_FREQ_24000MHZ 24000
1054
#define XTAL_FREQ_30000MHZ 30000
1055
#define XTAL_FREQ_37400MHZ 37400
1056
#define XTAL_FREQ_48000MHZ 48000
1058
static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = {
1060
12000, 1, 1, 1, 0x50, 0x0}, {
1061
13000, 2, 1, 1, 0x49, 0xD89D89}, {
1062
14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
1063
15360, 4, 1, 1, 0x3E, 0x800000}, {
1064
16200, 5, 1, 1, 0x39, 0x425ED0}, {
1065
16800, 6, 1, 1, 0x39, 0x249249}, {
1066
19200, 7, 1, 1, 0x32, 0x0}, {
1067
19800, 8, 1, 1, 0x30, 0x7C1F07}, {
1068
20000, 9, 1, 1, 0x30, 0x0}, {
1069
25000, 10, 1, 1, 0x26, 0x666666}, {
1070
26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
1071
30000, 12, 1, 1, 0x20, 0x0}, {
1072
37400, 13, 2, 1, 0x33, 0x563EF9}, {
1073
38400, 14, 2, 1, 0x32, 0x0}, {
1074
40000, 15, 2, 1, 0x30, 0x0}, {
1075
48000, 16, 2, 1, 0x28, 0x0}, {
1080
#define PMU1_XTALTAB0_960_12000K 0
1081
#define PMU1_XTALTAB0_960_13000K 1
1082
#define PMU1_XTALTAB0_960_14400K 2
1083
#define PMU1_XTALTAB0_960_15360K 3
1084
#define PMU1_XTALTAB0_960_16200K 4
1085
#define PMU1_XTALTAB0_960_16800K 5
1086
#define PMU1_XTALTAB0_960_19200K 6
1087
#define PMU1_XTALTAB0_960_19800K 7
1088
#define PMU1_XTALTAB0_960_20000K 8
1089
#define PMU1_XTALTAB0_960_25000K 9
1090
#define PMU1_XTALTAB0_960_26000K 10
1091
#define PMU1_XTALTAB0_960_30000K 11
1092
#define PMU1_XTALTAB0_960_37400K 12
1093
#define PMU1_XTALTAB0_960_38400K 13
1094
#define PMU1_XTALTAB0_960_40000K 14
1095
#define PMU1_XTALTAB0_960_48000K 15
1097
/* select xtal table for each chip */
1098
static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
1103
switch (sih->chip) {
1104
case BCM4329_CHIP_ID:
1105
return pmu1_xtaltab0_880_4329;
1106
case BCM4319_CHIP_ID:
1107
return pmu1_xtaltab0_1440;
1108
case BCM4336_CHIP_ID:
1109
return pmu1_xtaltab0_960;
1110
case BCM4330_CHIP_ID:
1111
if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1112
return pmu1_xtaltab0_960;
1114
return pmu1_xtaltab0_1440;
1116
PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n",
1117
bcm_chipname(sih->chip, chn, 8)));
1124
/* select default xtal frequency for each chip */
1125
static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
1131
switch (sih->chip) {
1132
case BCM4329_CHIP_ID:
1133
/* Default to 38400Khz */
1134
return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
1135
case BCM4319_CHIP_ID:
1136
/* Default to 30000Khz */
1137
return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
1138
case BCM4336_CHIP_ID:
1139
/* Default to 26000Khz */
1140
return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
1141
case BCM4330_CHIP_ID:
1142
/* Default to 37400Khz */
1143
if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1144
return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
1146
return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
1148
PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n",
1149
bcm_chipname(sih->chip, chn, 8)));
1156
/* select default pll fvco for each chip */
1157
static u32 si_pmu1_pllfvco0(si_t *sih)
1163
switch (sih->chip) {
1164
case BCM4329_CHIP_ID:
1166
case BCM4319_CHIP_ID:
1168
case BCM4336_CHIP_ID:
1170
case BCM4330_CHIP_ID:
1171
if (CST4330_CHIPMODE_SDIOD(sih->chipst))
1176
PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n",
1177
bcm_chipname(sih->chip, chn, 8)));
1184
/* query alp/xtal clock frequency */
1186
si_pmu1_alpclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc)
1188
const pmu1_xtaltab0_t *xt;
1191
/* Find the frequency in the table */
1192
xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
1193
PCTL_XTALFREQ_SHIFT;
1194
for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
1197
/* Could not find it so assign a default value */
1198
if (xt == NULL || xt->fref == 0)
1199
xt = si_pmu1_xtaldef0(sih);
1200
ASSERT(xt != NULL && xt->fref != 0);
1202
return xt->fref * 1000;
1205
/* Set up PLL registers in the PMU as per the crystal speed.
1206
* XtalFreq field in pmucontrol register being 0 indicates the PLL
1207
* is not programmed and the h/w default is assumed to work, in which
1208
* case the xtal frequency is unknown to the s/w so we need to call
1209
* si_pmu1_xtaldef0() wherever it is needed to return a default value.
1211
static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
1214
const pmu1_xtaltab0_t *xt;
1216
u32 buf_strength = 0;
1219
/* Use h/w default PLL config */
1221
PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
1225
/* Find the frequency in the table */
1226
for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
1227
if (xt->fref == xtal)
1230
/* Check current PLL state, bail out if it has been programmed or
1231
* we don't know how to program it.
1233
if (xt == NULL || xt->fref == 0) {
1234
PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n", xtal / 1000, xtal % 1000));
1237
/* for 4319 bootloader already programs the PLL but bootloader does not program the
1238
PLL4 and PLL5. So Skip this check for 4319
1240
if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
1241
PCTL_XTALFREQ_SHIFT) == xt->xf) &&
1242
!((sih->chip == BCM4319_CHIP_ID)
1243
|| (sih->chip == BCM4330_CHIP_ID))) {
1244
PMU_MSG(("PLL already programmed for %d.%d MHz\n",
1245
xt->fref / 1000, xt->fref % 1000));
1249
PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
1250
PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000,
1253
switch (sih->chip) {
1254
case BCM4329_CHIP_ID:
1255
/* Change the BBPLL drive strength to 8 for all channels */
1256
buf_strength = 0x888888;
1257
AND_REG(osh, &cc->min_res_mask,
1258
~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
1259
PMURES_BIT(RES4329_HT_AVAIL)));
1260
AND_REG(osh, &cc->max_res_mask,
1261
~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
1262
PMURES_BIT(RES4329_HT_AVAIL)));
1263
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1264
PMU_MAX_TRANSITION_DLY);
1265
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1266
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
1267
if (xt->fref == 38400)
1269
else if (xt->fref == 37400)
1271
else if (xt->fref == 26000)
1274
tmp = 0x200005C0; /* Chip Dflt Settings */
1275
W_REG(osh, &cc->pllcontrol_data, tmp);
1276
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
1279
&cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
1280
if ((xt->fref == 38400) || (xt->fref == 37400)
1281
|| (xt->fref == 26000))
1284
tmp |= 0x25; /* Chip Dflt Settings */
1285
W_REG(osh, &cc->pllcontrol_data, tmp);
1288
case BCM4319_CHIP_ID:
1289
/* Change the BBPLL drive strength to 2 for all channels */
1290
buf_strength = 0x222222;
1292
/* Make sure the PLL is off */
1293
/* WAR65104: Disable the HT_AVAIL resource first and then
1294
* after a delay (more than downtime for HT_AVAIL) remove the
1295
* BBPLL resource; backplane clock moves to ALP from HT.
1297
AND_REG(osh, &cc->min_res_mask,
1298
~(PMURES_BIT(RES4319_HT_AVAIL)));
1299
AND_REG(osh, &cc->max_res_mask,
1300
~(PMURES_BIT(RES4319_HT_AVAIL)));
1303
AND_REG(osh, &cc->min_res_mask,
1304
~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
1305
AND_REG(osh, &cc->max_res_mask,
1306
~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
1309
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1310
PMU_MAX_TRANSITION_DLY);
1311
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1312
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
1314
W_REG(osh, &cc->pllcontrol_data, tmp);
1317
case BCM4336_CHIP_ID:
1318
AND_REG(osh, &cc->min_res_mask,
1319
~(PMURES_BIT(RES4336_HT_AVAIL) |
1320
PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
1321
AND_REG(osh, &cc->max_res_mask,
1322
~(PMURES_BIT(RES4336_HT_AVAIL) |
1323
PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
1325
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1326
PMU_MAX_TRANSITION_DLY);
1327
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1330
case BCM4330_CHIP_ID:
1331
AND_REG(osh, &cc->min_res_mask,
1332
~(PMURES_BIT(RES4330_HT_AVAIL) |
1333
PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
1334
AND_REG(osh, &cc->max_res_mask,
1335
~(PMURES_BIT(RES4330_HT_AVAIL) |
1336
PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
1338
SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
1339
PMU_MAX_TRANSITION_DLY);
1340
ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
1347
PMU_MSG(("Done masking\n"));
1349
/* Write p1div and p2div to pllcontrol[0] */
1350
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
1351
tmp = R_REG(osh, &cc->pllcontrol_data) &
1352
~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
1355
p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
1357
p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
1358
W_REG(osh, &cc->pllcontrol_data, tmp);
1360
if ((sih->chip == BCM4330_CHIP_ID))
1361
si_pmu_set_4330_plldivs(sih);
1363
if ((sih->chip == BCM4329_CHIP_ID)
1364
&& (sih->chiprev == 0)) {
1366
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
1367
tmp = R_REG(osh, &cc->pllcontrol_data);
1368
tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
1369
tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
1370
W_REG(osh, &cc->pllcontrol_data, tmp);
1372
if ((sih->chip == BCM4319_CHIP_ID) ||
1373
(sih->chip == BCM4336_CHIP_ID) ||
1374
(sih->chip == BCM4330_CHIP_ID))
1375
ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
1377
ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
1379
/* Write ndiv_int and ndiv_mode to pllcontrol[2] */
1380
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
1381
tmp = R_REG(osh, &cc->pllcontrol_data) &
1382
~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
1385
ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
1386
PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
1387
PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
1388
PMU1_PLL0_PC2_NDIV_MODE_MASK);
1389
W_REG(osh, &cc->pllcontrol_data, tmp);
1391
/* Write ndiv_frac to pllcontrol[3] */
1392
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
1393
tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
1394
tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
1395
PMU1_PLL0_PC3_NDIV_FRAC_MASK);
1396
W_REG(osh, &cc->pllcontrol_data, tmp);
1398
/* Write clock driving strength to pllcontrol[5] */
1400
PMU_MSG(("Adjusting PLL buffer drive strength: %x\n",
1403
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
1406
&cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
1407
tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
1408
W_REG(osh, &cc->pllcontrol_data, tmp);
1411
PMU_MSG(("Done pll\n"));
1413
/* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
1416
if ((sih->chip == BCM4319_CHIP_ID)
1417
&& (xt->fref != XTAL_FREQ_30000MHZ)) {
1418
W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
1421
&cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
1422
if (xt->fref == XTAL_FREQ_24000MHZ) {
1424
(CCTL_4319USB_24MHZ_PLL_SEL <<
1425
CCTL_4319USB_XTAL_SEL_SHIFT);
1426
} else if (xt->fref == XTAL_FREQ_48000MHZ) {
1428
(CCTL_4319USB_48MHZ_PLL_SEL <<
1429
CCTL_4319USB_XTAL_SEL_SHIFT);
1431
W_REG(osh, &cc->chipcontrol_data, tmp);
1434
/* Flush deferred pll control registers writes */
1435
if (sih->pmurev >= 2)
1436
OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
1438
/* Write XtalFreq. Set the divisor also. */
1439
tmp = R_REG(osh, &cc->pmucontrol) &
1440
~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
1441
tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
1442
PCTL_ILP_DIV_MASK) |
1443
((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
1445
if ((sih->chip == BCM4329_CHIP_ID)
1446
&& sih->chiprev == 0) {
1447
/* clear the htstretch before clearing HTReqEn */
1448
AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
1449
tmp &= ~PCTL_HT_REQ_EN;
1452
W_REG(osh, &cc->pmucontrol, tmp);
1455
/* query the CPU clock frequency */
1457
si_pmu1_cpuclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc)
1461
u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
1464
u32 FVCO = si_pmu1_pllfvco0(sih);
1466
/* Read m1div from pllcontrol[1] */
1467
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
1468
tmp = R_REG(osh, &cc->pllcontrol_data);
1469
m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT;
1472
/* Read p2div/p1div from pllcontrol[0] */
1473
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
1474
tmp = R_REG(osh, &cc->pllcontrol_data);
1475
p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT;
1476
p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT;
1478
/* Calculate fvco based on xtal freq and ndiv and pdiv */
1479
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
1480
tmp = R_REG(osh, &cc->pllcontrol_data);
1482
(tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT;
1484
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
1485
tmp = R_REG(osh, &cc->pllcontrol_data);
1487
(tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >>
1488
PMU1_PLL0_PC3_NDIV_FRAC_SHIFT;
1490
fref = si_pmu1_alpclk0(sih, osh, cc) / 1000;
1492
fvco = (fref * ndiv_int) << 8;
1493
fvco += (fref * (ndiv_frac >> 12)) >> 4;
1494
fvco += (fref * (ndiv_frac & 0xfff)) >> 12;
1501
PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco));
1506
/* Return ARM/SB clock */
1507
return FVCO / m1div * 1000;
1510
/* initialize PLL */
1511
void si_pmu_pll_init(si_t *sih, struct osl_info *osh, uint xtalfreq)
1519
ASSERT(sih->cccaps & CC_CAP_PMU);
1521
/* Remember original core before switch to chipc */
1522
origidx = si_coreidx(sih);
1523
cc = si_setcoreidx(sih, SI_CC_IDX);
1526
switch (sih->chip) {
1527
case BCM4329_CHIP_ID:
1530
si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
1532
case BCM4313_CHIP_ID:
1533
case BCM43224_CHIP_ID:
1534
case BCM43225_CHIP_ID:
1535
case BCM43421_CHIP_ID:
1536
case BCM43235_CHIP_ID:
1537
case BCM43236_CHIP_ID:
1538
case BCM43238_CHIP_ID:
1539
case BCM4331_CHIP_ID:
1540
case BCM6362_CHIP_ID:
1543
case BCM4319_CHIP_ID:
1544
case BCM4336_CHIP_ID:
1545
case BCM4330_CHIP_ID:
1546
si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
1549
PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n",
1550
bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1555
#ifdef BCMDBG_FORCEHT
1556
OR_REG(osh, &cc->clk_ctl_st, CCS_FORCEHT);
1559
/* Return to original core */
1560
si_setcoreidx(sih, origidx);
1563
/* query alp/xtal clock frequency */
1564
u32 si_pmu_alp_clock(si_t *sih, struct osl_info *osh)
1568
u32 clock = ALP_CLOCK;
1573
ASSERT(sih->cccaps & CC_CAP_PMU);
1575
/* Remember original core before switch to chipc */
1576
origidx = si_coreidx(sih);
1577
cc = si_setcoreidx(sih, SI_CC_IDX);
1580
switch (sih->chip) {
1581
case BCM43224_CHIP_ID:
1582
case BCM43225_CHIP_ID:
1583
case BCM43421_CHIP_ID:
1584
case BCM43235_CHIP_ID:
1585
case BCM43236_CHIP_ID:
1586
case BCM43238_CHIP_ID:
1587
case BCM4331_CHIP_ID:
1588
case BCM6362_CHIP_ID:
1589
case BCM4716_CHIP_ID:
1590
case BCM4748_CHIP_ID:
1591
case BCM47162_CHIP_ID:
1592
case BCM4313_CHIP_ID:
1593
case BCM5357_CHIP_ID:
1595
clock = 20000 * 1000;
1597
case BCM4329_CHIP_ID:
1598
case BCM4319_CHIP_ID:
1599
case BCM4336_CHIP_ID:
1600
case BCM4330_CHIP_ID:
1602
clock = si_pmu1_alpclk0(sih, osh, cc);
1604
case BCM5356_CHIP_ID:
1606
clock = 25000 * 1000;
1609
PMU_MSG(("No ALP clock specified "
1610
"for chip %s rev %d pmurev %d, using default %d Hz\n",
1611
bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1612
sih->pmurev, clock));
1616
/* Return to original core */
1617
si_setcoreidx(sih, origidx);
1621
/* Find the output of the "m" pll divider given pll controls that start with
1622
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
1625
si_pmu5_clock(si_t *sih, struct osl_info *osh, chipcregs_t *cc, uint pll0,
1627
u32 tmp, div, ndiv, p1, p2, fc;
1629
if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
1630
PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0));
1634
/* Strictly there is an m5 divider, but I'm not sure we use it */
1635
if ((m == 0) || (m > 4)) {
1636
PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m));
1640
if (sih->chip == BCM5357_CHIP_ID) {
1641
/* Detect failure in clock setting */
1642
if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) {
1643
return 133 * 1000000;
1647
W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF);
1648
(void)R_REG(osh, &cc->pllcontrol_addr);
1649
tmp = R_REG(osh, &cc->pllcontrol_data);
1650
p1 = (tmp & PMU5_PLL_P1_MASK) >> PMU5_PLL_P1_SHIFT;
1651
p2 = (tmp & PMU5_PLL_P2_MASK) >> PMU5_PLL_P2_SHIFT;
1653
W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF);
1654
(void)R_REG(osh, &cc->pllcontrol_addr);
1655
tmp = R_REG(osh, &cc->pllcontrol_data);
1656
div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK;
1658
W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF);
1659
(void)R_REG(osh, &cc->pllcontrol_addr);
1660
tmp = R_REG(osh, &cc->pllcontrol_data);
1661
ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT;
1663
/* Do calculation in Mhz */
1664
fc = si_pmu_alp_clock(sih, osh) / 1000000;
1665
fc = (p1 * ndiv * fc) / p2;
1667
PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n",
1668
__func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div));
1670
/* Return clock in Hertz */
1671
return (fc / div) * 1000000;
1674
/* query backplane clock frequency */
1675
/* For designs that feed the same clock to both backplane
1676
* and CPU just return the CPU clock speed.
1678
u32 si_pmu_si_clock(si_t *sih, struct osl_info *osh)
1682
u32 clock = HT_CLOCK;
1687
ASSERT(sih->cccaps & CC_CAP_PMU);
1689
/* Remember original core before switch to chipc */
1690
origidx = si_coreidx(sih);
1691
cc = si_setcoreidx(sih, SI_CC_IDX);
1694
switch (sih->chip) {
1695
case BCM43224_CHIP_ID:
1696
case BCM43225_CHIP_ID:
1697
case BCM43421_CHIP_ID:
1698
case BCM4331_CHIP_ID:
1699
case BCM6362_CHIP_ID:
1700
/* 96MHz backplane clock */
1701
clock = 96000 * 1000;
1703
case BCM4716_CHIP_ID:
1704
case BCM4748_CHIP_ID:
1705
case BCM47162_CHIP_ID:
1707
si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0,
1710
case BCM4329_CHIP_ID:
1711
if (sih->chiprev == 0)
1712
clock = 38400 * 1000;
1714
clock = si_pmu1_cpuclk0(sih, osh, cc);
1716
case BCM4319_CHIP_ID:
1717
case BCM4336_CHIP_ID:
1718
case BCM4330_CHIP_ID:
1719
clock = si_pmu1_cpuclk0(sih, osh, cc);
1721
case BCM4313_CHIP_ID:
1722
/* 80MHz backplane clock */
1723
clock = 80000 * 1000;
1725
case BCM43235_CHIP_ID:
1726
case BCM43236_CHIP_ID:
1727
case BCM43238_CHIP_ID:
1729
(cc->chipstatus & CST43236_BP_CLK) ? (120000 *
1733
case BCM5356_CHIP_ID:
1735
si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0,
1738
case BCM5357_CHIP_ID:
1740
si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0,
1744
PMU_MSG(("No backplane clock specified "
1745
"for chip %s rev %d pmurev %d, using default %d Hz\n",
1746
bcm_chipname(sih->chip, chn, 8), sih->chiprev,
1747
sih->pmurev, clock));
1751
/* Return to original core */
1752
si_setcoreidx(sih, origidx);
1756
/* query CPU clock frequency */
1757
u32 si_pmu_cpu_clock(si_t *sih, struct osl_info *osh)
1763
ASSERT(sih->cccaps & CC_CAP_PMU);
1765
if ((sih->pmurev >= 5) &&
1766
!((sih->chip == BCM4329_CHIP_ID) ||
1767
(sih->chip == BCM4319_CHIP_ID) ||
1768
(sih->chip == BCM43236_CHIP_ID) ||
1769
(sih->chip == BCM4336_CHIP_ID) ||
1770
(sih->chip == BCM4330_CHIP_ID))) {
1773
switch (sih->chip) {
1774
case BCM5356_CHIP_ID:
1775
pll = PMU5356_MAINPLL_PLL0;
1777
case BCM5357_CHIP_ID:
1778
pll = PMU5357_MAINPLL_PLL0;
1781
pll = PMU4716_MAINPLL_PLL0;
1785
/* Remember original core before switch to chipc */
1786
origidx = si_coreidx(sih);
1787
cc = si_setcoreidx(sih, SI_CC_IDX);
1790
clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU);
1792
/* Return to original core */
1793
si_setcoreidx(sih, origidx);
1795
clock = si_pmu_si_clock(sih, osh);
1800
/* query memory clock frequency */
1801
u32 si_pmu_mem_clock(si_t *sih, struct osl_info *osh)
1807
ASSERT(sih->cccaps & CC_CAP_PMU);
1809
if ((sih->pmurev >= 5) &&
1810
!((sih->chip == BCM4329_CHIP_ID) ||
1811
(sih->chip == BCM4319_CHIP_ID) ||
1812
(sih->chip == BCM4330_CHIP_ID) ||
1813
(sih->chip == BCM4336_CHIP_ID) ||
1814
(sih->chip == BCM43236_CHIP_ID))) {
1817
switch (sih->chip) {
1818
case BCM5356_CHIP_ID:
1819
pll = PMU5356_MAINPLL_PLL0;
1821
case BCM5357_CHIP_ID:
1822
pll = PMU5357_MAINPLL_PLL0;
1825
pll = PMU4716_MAINPLL_PLL0;
1829
/* Remember original core before switch to chipc */
1830
origidx = si_coreidx(sih);
1831
cc = si_setcoreidx(sih, SI_CC_IDX);
1834
clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM);
1836
/* Return to original core */
1837
si_setcoreidx(sih, origidx);
1839
clock = si_pmu_si_clock(sih, osh);
1845
/* Measure ILP clock frequency */
1846
#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */
1848
static u32 ilpcycles_per_sec;
1850
u32 si_pmu_ilp_clock(si_t *sih, struct osl_info *osh)
1852
if (ISSIM_ENAB(sih))
1855
if (ilpcycles_per_sec == 0) {
1856
u32 start, end, delta;
1857
u32 origidx = si_coreidx(sih);
1858
chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
1860
start = R_REG(osh, &cc->pmutimer);
1861
mdelay(ILP_CALC_DUR);
1862
end = R_REG(osh, &cc->pmutimer);
1863
delta = end - start;
1864
ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
1865
si_setcoreidx(sih, origidx);
1868
return ilpcycles_per_sec;
1871
/* SDIO Pad drive strength to select value mappings */
1873
u8 strength; /* Pad Drive Strength in mA */
1874
u8 sel; /* Chip-specific select value */
1875
} sdiod_drive_str_t;
1877
/* SDIO Drive Strength to sel value table for PMU Rev 1 */
1878
static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
1886
/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
1887
static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
1898
/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
1899
static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
1911
#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
1914
si_sdiod_drive_strength_init(si_t *sih, struct osl_info *osh,
1915
u32 drivestrength) {
1917
uint origidx, intr_val = 0;
1918
sdiod_drive_str_t *str_tab = NULL;
1925
if (!(sih->cccaps & CC_CAP_PMU)) {
1929
/* Remember original core before switch to chipc */
1930
cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
1933
switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
1934
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
1935
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
1936
str_mask = 0x30000000;
1939
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
1940
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
1941
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
1942
str_mask = 0x00003800;
1945
case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
1946
str_tab = (sdiod_drive_str_t *) &sdiod_drive_strength_tab3;
1947
str_mask = 0x00003800;
1952
PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
1957
if (str_tab != NULL) {
1958
u32 drivestrength_sel = 0;
1962
for (i = 0; str_tab[i].strength != 0; i++) {
1963
if (drivestrength >= str_tab[i].strength) {
1964
drivestrength_sel = str_tab[i].sel;
1969
W_REG(osh, &cc->chipcontrol_addr, 1);
1970
cc_data_temp = R_REG(osh, &cc->chipcontrol_data);
1971
cc_data_temp &= ~str_mask;
1972
drivestrength_sel <<= str_shift;
1973
cc_data_temp |= drivestrength_sel;
1974
W_REG(osh, &cc->chipcontrol_data, cc_data_temp);
1976
PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
1977
drivestrength, cc_data_temp));
1980
/* Return to original core */
1981
si_restore_core(sih, origidx, intr_val);
1984
/* initialize PMU */
1985
void si_pmu_init(si_t *sih, struct osl_info *osh)
1990
ASSERT(sih->cccaps & CC_CAP_PMU);
1992
/* Remember original core before switch to chipc */
1993
origidx = si_coreidx(sih);
1994
cc = si_setcoreidx(sih, SI_CC_IDX);
1997
if (sih->pmurev == 1)
1998
AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
1999
else if (sih->pmurev >= 2)
2000
OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT);
2002
if ((sih->chip == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
2003
/* Fix for 4329b0 bad LPOM state. */
2004
W_REG(osh, &cc->regcontrol_addr, 2);
2005
OR_REG(osh, &cc->regcontrol_data, 0x100);
2007
W_REG(osh, &cc->regcontrol_addr, 3);
2008
OR_REG(osh, &cc->regcontrol_data, 0x4);
2011
/* Return to original core */
2012
si_setcoreidx(sih, origidx);
2015
/* Return up time in ILP cycles for the given resource. */
2017
si_pmu_res_uptime(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
2020
uint up, i, dup, dmax;
2021
u32 min_mask = 0, max_mask = 0;
2023
/* uptime of resource 'rsrc' */
2024
W_REG(osh, &cc->res_table_sel, rsrc);
2025
up = (R_REG(osh, &cc->res_updn_timer) >> 8) & 0xff;
2027
/* direct dependancies of resource 'rsrc' */
2028
deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), false);
2029
for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2030
if (!(deps & PMURES_BIT(i)))
2032
deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), true);
2034
si_pmu_res_masks(sih, &min_mask, &max_mask);
2037
/* max uptime of direct dependancies */
2039
for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2040
if (!(deps & PMURES_BIT(i)))
2042
dup = si_pmu_res_uptime(sih, osh, cc, (u8) i);
2047
PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", rsrc, up, deps, dmax));
2049
return up + dmax + PMURES_UP_TRANSITION;
2052
/* Return dependancies (direct or all/indirect) for the given resources */
2054
si_pmu_res_deps(si_t *sih, struct osl_info *osh, chipcregs_t *cc, u32 rsrcs,
2060
for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2061
if (!(rsrcs & PMURES_BIT(i)))
2063
W_REG(osh, &cc->res_table_sel, i);
2064
deps |= R_REG(osh, &cc->res_dep_mask);
2067
return !all ? deps : (deps
2069
si_pmu_res_deps(sih, osh, cc, deps,
2073
/* power up/down OTP through PMU resources */
2074
void si_pmu_otp_power(si_t *sih, struct osl_info *osh, bool on)
2078
u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
2080
ASSERT(sih->cccaps & CC_CAP_PMU);
2082
/* Don't do anything if OTP is disabled */
2083
if (si_is_otp_disabled(sih)) {
2084
PMU_MSG(("si_pmu_otp_power: OTP is disabled\n"));
2088
/* Remember original core before switch to chipc */
2089
origidx = si_coreidx(sih);
2090
cc = si_setcoreidx(sih, SI_CC_IDX);
2093
switch (sih->chip) {
2094
case BCM4329_CHIP_ID:
2095
rsrcs = PMURES_BIT(RES4329_OTP_PU);
2097
case BCM4319_CHIP_ID:
2098
rsrcs = PMURES_BIT(RES4319_OTP_PU);
2100
case BCM4336_CHIP_ID:
2101
rsrcs = PMURES_BIT(RES4336_OTP_PU);
2103
case BCM4330_CHIP_ID:
2104
rsrcs = PMURES_BIT(RES4330_OTP_PU);
2113
/* Figure out the dependancies (exclude min_res_mask) */
2114
u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, true);
2115
u32 min_mask = 0, max_mask = 0;
2116
si_pmu_res_masks(sih, &min_mask, &max_mask);
2118
/* Turn on/off the power */
2120
PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n",
2122
OR_REG(osh, &cc->min_res_mask, (rsrcs | deps));
2123
SPINWAIT(!(R_REG(osh, &cc->res_state) & rsrcs),
2124
PMU_MAX_TRANSITION_DLY);
2125
ASSERT(R_REG(osh, &cc->res_state) & rsrcs);
2127
PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n",
2129
AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps));
2132
SPINWAIT((((otps = R_REG(osh, &cc->otpstatus)) & OTPS_READY) !=
2133
(on ? OTPS_READY : 0)), 100);
2134
ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0));
2135
if ((otps & OTPS_READY) != (on ? OTPS_READY : 0))
2136
PMU_MSG(("OTP ready bit not %s after wait\n",
2137
(on ? "ON" : "OFF")));
2140
/* Return to original core */
2141
si_setcoreidx(sih, origidx);
2144
void si_pmu_rcal(si_t *sih, struct osl_info *osh)
2149
ASSERT(sih->cccaps & CC_CAP_PMU);
2151
/* Remember original core before switch to chipc */
2152
origidx = si_coreidx(sih);
2153
cc = si_setcoreidx(sih, SI_CC_IDX);
2156
switch (sih->chip) {
2157
case BCM4329_CHIP_ID:{
2162
W_REG(osh, &cc->chipcontrol_addr, 1);
2164
/* Power Down RCAL Block */
2165
AND_REG(osh, &cc->chipcontrol_data, ~0x04);
2167
/* Power Up RCAL block */
2168
OR_REG(osh, &cc->chipcontrol_data, 0x04);
2170
/* Wait for completion */
2171
SPINWAIT(0 == (R_REG(osh, &cc->chipstatus) & 0x08),
2173
ASSERT(R_REG(osh, &cc->chipstatus) & 0x08);
2175
/* Drop the LSB to convert from 5 bit code to 4 bit code */
2177
(u8) (R_REG(osh, &cc->chipstatus) >> 5) & 0x0f;
2179
PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n",
2180
R_REG(osh, &cc->chipstatus), rcal_code));
2182
/* Write RCal code into pmu_vreg_ctrl[32:29] */
2183
W_REG(osh, &cc->regcontrol_addr, 0);
2187
regcontrol_data) & ~((u32) 0x07 << 29);
2188
val |= (u32) (rcal_code & 0x07) << 29;
2189
W_REG(osh, &cc->regcontrol_data, val);
2190
W_REG(osh, &cc->regcontrol_addr, 1);
2191
val = R_REG(osh, &cc->regcontrol_data) & ~(u32) 0x01;
2192
val |= (u32) ((rcal_code >> 3) & 0x01);
2193
W_REG(osh, &cc->regcontrol_data, val);
2195
/* Write RCal code into pmu_chip_ctrl[33:30] */
2196
W_REG(osh, &cc->chipcontrol_addr, 0);
2200
chipcontrol_data) & ~((u32) 0x03 << 30);
2201
val |= (u32) (rcal_code & 0x03) << 30;
2202
W_REG(osh, &cc->chipcontrol_data, val);
2203
W_REG(osh, &cc->chipcontrol_addr, 1);
2205
R_REG(osh, &cc->chipcontrol_data) & ~(u32) 0x03;
2206
val |= (u32) ((rcal_code >> 2) & 0x03);
2207
W_REG(osh, &cc->chipcontrol_data, val);
2209
/* Set override in pmu_chip_ctrl[29] */
2210
W_REG(osh, &cc->chipcontrol_addr, 0);
2211
OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29));
2213
/* Power off RCal block */
2214
W_REG(osh, &cc->chipcontrol_addr, 1);
2215
AND_REG(osh, &cc->chipcontrol_data, ~0x04);
2223
/* Return to original core */
2224
si_setcoreidx(sih, origidx);
2227
void si_pmu_spuravoid(si_t *sih, struct osl_info *osh, u8 spuravoid)
2230
uint origidx, intr_val;
2233
/* Remember original core before switch to chipc */
2234
cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
2238
/* force the HT off */
2239
if (sih->chip == BCM4336_CHIP_ID) {
2240
tmp = R_REG(osh, &cc->max_res_mask);
2241
tmp &= ~RES4336_HT_AVAIL;
2242
W_REG(osh, &cc->max_res_mask, tmp);
2243
/* wait for the ht to really go away */
2244
SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
2246
ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == 0);
2249
/* update the pll changes */
2250
si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
2252
/* enable HT back on */
2253
if (sih->chip == BCM4336_CHIP_ID) {
2254
tmp = R_REG(osh, &cc->max_res_mask);
2255
tmp |= RES4336_HT_AVAIL;
2256
W_REG(osh, &cc->max_res_mask, tmp);
2259
/* Return to original core */
2260
si_restore_core(sih, origidx, intr_val);
2264
si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, struct osl_info *osh,
2268
u8 phypll_offset = 0;
2269
u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
2270
u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
2272
switch (sih->chip) {
2273
case BCM5357_CHIP_ID:
2274
case BCM43235_CHIP_ID:
2275
case BCM43236_CHIP_ID:
2276
case BCM43238_CHIP_ID:
2278
/* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */
2279
phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
2281
/* RMW only the P1 divider */
2282
W_REG(osh, &cc->pllcontrol_addr,
2283
PMU1_PLL0_PLLCTL0 + phypll_offset);
2284
tmp = R_REG(osh, &cc->pllcontrol_data);
2285
tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
2287
(bcm5357_bcm43236_p1div[spuravoid] <<
2288
PMU1_PLL0_PC0_P1DIV_SHIFT);
2289
W_REG(osh, &cc->pllcontrol_data, tmp);
2291
/* RMW only the int feedback divider */
2292
W_REG(osh, &cc->pllcontrol_addr,
2293
PMU1_PLL0_PLLCTL2 + phypll_offset);
2294
tmp = R_REG(osh, &cc->pllcontrol_data);
2295
tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
2297
(bcm5357_bcm43236_ndiv[spuravoid]) <<
2298
PMU1_PLL0_PC2_NDIV_INT_SHIFT;
2299
W_REG(osh, &cc->pllcontrol_data, tmp);
2304
case BCM4331_CHIP_ID:
2305
if (spuravoid == 2) {
2306
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2307
W_REG(osh, &cc->pllcontrol_data, 0x11500014);
2308
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2309
W_REG(osh, &cc->pllcontrol_data, 0x0FC00a08);
2310
} else if (spuravoid == 1) {
2311
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2312
W_REG(osh, &cc->pllcontrol_data, 0x11500014);
2313
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2314
W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
2316
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2317
W_REG(osh, &cc->pllcontrol_data, 0x11100014);
2318
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2319
W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2324
case BCM43224_CHIP_ID:
2325
case BCM43225_CHIP_ID:
2326
case BCM43421_CHIP_ID:
2327
case BCM6362_CHIP_ID:
2328
if (spuravoid == 1) {
2329
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2330
W_REG(osh, &cc->pllcontrol_data, 0x11500010);
2331
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2332
W_REG(osh, &cc->pllcontrol_data, 0x000C0C06);
2333
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2334
W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
2335
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2336
W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2337
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2338
W_REG(osh, &cc->pllcontrol_data, 0x2001E920);
2339
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2340
W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2342
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2343
W_REG(osh, &cc->pllcontrol_data, 0x11100010);
2344
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2345
W_REG(osh, &cc->pllcontrol_data, 0x000c0c06);
2346
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2347
W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2348
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2349
W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2350
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2351
W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2352
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2353
W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2358
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2359
W_REG(osh, &cc->pllcontrol_data, 0x11100008);
2360
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2361
W_REG(osh, &cc->pllcontrol_data, 0x0c000c06);
2362
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2363
W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
2364
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2365
W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2366
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2367
W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2368
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2369
W_REG(osh, &cc->pllcontrol_data, 0x88888855);
2374
case BCM4716_CHIP_ID:
2375
case BCM4748_CHIP_ID:
2376
case BCM47162_CHIP_ID:
2377
if (spuravoid == 1) {
2378
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2379
W_REG(osh, &cc->pllcontrol_data, 0x11500060);
2380
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2381
W_REG(osh, &cc->pllcontrol_data, 0x080C0C06);
2382
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2383
W_REG(osh, &cc->pllcontrol_data, 0x0F600000);
2384
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2385
W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2386
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2387
W_REG(osh, &cc->pllcontrol_data, 0x2001E924);
2388
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2389
W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2391
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2392
W_REG(osh, &cc->pllcontrol_data, 0x11100060);
2393
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2394
W_REG(osh, &cc->pllcontrol_data, 0x080c0c06);
2395
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2396
W_REG(osh, &cc->pllcontrol_data, 0x03000000);
2397
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2398
W_REG(osh, &cc->pllcontrol_data, 0x00000000);
2399
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2400
W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
2401
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2402
W_REG(osh, &cc->pllcontrol_data, 0x88888815);
2408
case BCM4319_CHIP_ID:
2409
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2410
W_REG(osh, &cc->pllcontrol_data, 0x11100070);
2411
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2412
W_REG(osh, &cc->pllcontrol_data, 0x1014140a);
2413
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2414
W_REG(osh, &cc->pllcontrol_data, 0x88888854);
2416
if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
2417
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2418
W_REG(osh, &cc->pllcontrol_data, 0x05201828);
2419
} else { /* enable 40/80/160Mhz clock mode */
2420
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2421
W_REG(osh, &cc->pllcontrol_data, 0x05001828);
2424
case BCM4336_CHIP_ID:
2425
/* Looks like these are only for default xtal freq 26MHz */
2426
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
2427
W_REG(osh, &cc->pllcontrol_data, 0x02100020);
2429
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
2430
W_REG(osh, &cc->pllcontrol_data, 0x0C0C0C0C);
2432
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
2433
W_REG(osh, &cc->pllcontrol_data, 0x01240C0C);
2435
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
2436
W_REG(osh, &cc->pllcontrol_data, 0x202C2820);
2438
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
2439
W_REG(osh, &cc->pllcontrol_data, 0x88888825);
2441
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
2442
if (spuravoid == 1) {
2443
W_REG(osh, &cc->pllcontrol_data, 0x00EC4EC4);
2445
W_REG(osh, &cc->pllcontrol_data, 0x00762762);
2448
tmp = PCTL_PLL_PLLCTL_UPD;
2452
PMU_ERROR(("%s: unknown spuravoidance settings for chip %s, not changing PLL\n", __func__, bcm_chipname(sih->chip, chn, 8)));
2456
tmp |= R_REG(osh, &cc->pmucontrol);
2457
W_REG(osh, &cc->pmucontrol, tmp);
2460
bool si_pmu_is_otp_powered(si_t *sih, struct osl_info *osh)
2466
/* Remember original core before switch to chipc */
2467
idx = si_coreidx(sih);
2468
cc = si_setcoreidx(sih, SI_CC_IDX);
2471
switch (sih->chip) {
2472
case BCM4329_CHIP_ID:
2473
st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
2476
case BCM4319_CHIP_ID:
2477
st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
2480
case BCM4336_CHIP_ID:
2481
st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
2484
case BCM4330_CHIP_ID:
2485
st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
2489
/* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
2490
* Use OTP_INIT command to reset/refresh state.
2492
case BCM43224_CHIP_ID:
2493
case BCM43225_CHIP_ID:
2494
case BCM43421_CHIP_ID:
2495
case BCM43236_CHIP_ID:
2496
case BCM43235_CHIP_ID:
2497
case BCM43238_CHIP_ID:
2505
/* Return to original core */
2506
si_setcoreidx(sih, idx);
2512
si_pmu_sprom_enable(si_t *sih, struct osl_info *osh, bool enable)
2514
si_pmu_sprom_enable(si_t *sih, struct osl_info *osh, bool enable)
2520
/* Remember original core before switch to chipc */
2521
origidx = si_coreidx(sih);
2522
cc = si_setcoreidx(sih, SI_CC_IDX);
2525
/* Return to original core */
2526
si_setcoreidx(sih, origidx);
2529
/* initialize PMU chip controls and other chip level stuff */
2530
void si_pmu_chip_init(si_t *sih, struct osl_info *osh)
2534
ASSERT(sih->cccaps & CC_CAP_PMU);
2536
#ifdef CHIPC_UART_ALWAYS_ON
2537
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, clk_ctl_st),
2538
CCS_FORCEALP, CCS_FORCEALP);
2539
#endif /* CHIPC_UART_ALWAYS_ON */
2541
/* Gate off SPROM clock and chip select signals */
2542
si_pmu_sprom_enable(sih, osh, false);
2544
/* Remember original core */
2545
origidx = si_coreidx(sih);
2547
/* Return to original core */
2548
si_setcoreidx(sih, origidx);
2551
/* initialize PMU switch/regulators */
2552
void si_pmu_swreg_init(si_t *sih, struct osl_info *osh)
2554
ASSERT(sih->cccaps & CC_CAP_PMU);
2556
switch (sih->chip) {
2557
case BCM4336_CHIP_ID:
2558
/* Reduce CLDO PWM output voltage to 1.2V */
2559
si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
2560
/* Reduce CLDO BURST output voltage to 1.2V */
2561
si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST,
2563
/* Reduce LNLDO1 output voltage to 1.2V */
2564
si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
2565
if (sih->chiprev == 0)
2566
si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
2569
case BCM4330_CHIP_ID:
2570
/* CBUCK Voltage is 1.8 by default and set that to 1.5 */
2571
si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
2578
void si_pmu_radio_enable(si_t *sih, bool enable)
2580
ASSERT(sih->cccaps & CC_CAP_PMU);
2582
switch (sih->chip) {
2583
case BCM4319_CHIP_ID:
2585
si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2588
si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2594
/* Wait for a particular clock level to be on the backplane */
2596
si_pmu_waitforclk_on_backplane(si_t *sih, struct osl_info *osh, u32 clk,
2602
ASSERT(sih->cccaps & CC_CAP_PMU);
2604
/* Remember original core before switch to chipc */
2605
origidx = si_coreidx(sih);
2606
cc = si_setcoreidx(sih, SI_CC_IDX);
2610
SPINWAIT(((R_REG(osh, &cc->pmustatus) & clk) != clk), delay);
2612
/* Return to original core */
2613
si_setcoreidx(sih, origidx);
2615
return R_REG(osh, &cc->pmustatus) & clk;
2619
* Measures the ALP clock frequency in KHz. Returns 0 if not possible.
2620
* Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal.
2623
#define EXT_ILP_HZ 32768
2625
u32 si_pmu_measure_alpclk(si_t *sih, struct osl_info *osh)
2631
if (sih->pmurev < 10)
2634
ASSERT(sih->cccaps & CC_CAP_PMU);
2636
/* Remember original core before switch to chipc */
2637
origidx = si_coreidx(sih);
2638
cc = si_setcoreidx(sih, SI_CC_IDX);
2641
if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) {
2642
u32 ilp_ctr, alp_hz;
2644
/* Enable the reg to measure the freq, in case disabled before */
2645
W_REG(osh, &cc->pmu_xtalfreq,
2646
1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
2648
/* Delay for well over 4 ILP clocks */
2651
/* Read the latched number of ALP ticks per 4 ILP ticks */
2654
&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
2656
/* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT bit to save power */
2657
W_REG(osh, &cc->pmu_xtalfreq, 0);
2659
/* Calculate ALP frequency */
2660
alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
2662
/* Round to nearest 100KHz, and at the same time convert to KHz */
2663
alp_khz = (alp_hz + 50000) / 100000 * 100;
2667
/* Return to original core */
2668
si_setcoreidx(sih, origidx);
2673
static void si_pmu_set_4330_plldivs(si_t *sih)
2675
u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
2676
u32 m1div, m2div, m3div, m4div, m5div, m6div;
2679
m2div = m3div = m4div = m6div = FVCO / 80;
2682
if (CST4330_CHIPMODE_SDIOD(sih->chipst))
2687
(m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
2688
PMU1_PLL0_PC1_M2DIV_SHIFT) |
2689
(m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
2690
PMU1_PLL0_PC1_M4DIV_SHIFT);
2691
si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
2693
pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
2694
pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
2696
((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
2697
(m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
2698
si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);
added
removed
drivers/staging/brcm80211/util/hndpmu.c
