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Viewing changes to drivers/gpu/drm/radeon/radeon_bios.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/gpu/drm/radeon/radeon_bios.c
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static bool radeon_atrm_get_bios(struct radeon_device *rdev)
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{
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        int ret;
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        int size = 64 * 1024;
 
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        int size = 256 * 1024;
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        int i;
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        if (!radeon_atrm_supported(rdev->pdev))
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        seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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        viph_control = RREG32(RADEON_VIPH_CONTROL);
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        bus_cntl = RREG32(RADEON_BUS_CNTL);
 
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        bus_cntl = RREG32(RV370_BUS_CNTL);
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        d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
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        d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
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        vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
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        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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        /* enable the rom */
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        WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
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        WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
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        /* Disable VGA mode */
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        WREG32(AVIVO_D1VGA_CONTROL,
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        /* restore regs */
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        WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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        WREG32(RADEON_VIPH_CONTROL, viph_control);
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        WREG32(RADEON_BUS_CNTL, bus_cntl);
 
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        WREG32(RV370_BUS_CNTL, bus_cntl);
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        WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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        WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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        WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
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        seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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        viph_control = RREG32(RADEON_VIPH_CONTROL);
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        bus_cntl = RREG32(RADEON_BUS_CNTL);
 
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        if (rdev->flags & RADEON_IS_PCIE)
 
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                bus_cntl = RREG32(RV370_BUS_CNTL);
 
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        else
 
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                bus_cntl = RREG32(RADEON_BUS_CNTL);
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        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
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        crtc2_gen_cntl = 0;
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        crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
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        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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        /* enable the rom */
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        WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
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        if (rdev->flags & RADEON_IS_PCIE)
 
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                WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 
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        else
 
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                WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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        /* Turn off mem requests and CRTC for both controllers */
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        WREG32(RADEON_CRTC_GEN_CNTL,
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        /* restore regs */
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        WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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        WREG32(RADEON_VIPH_CONTROL, viph_control);
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        WREG32(RADEON_BUS_CNTL, bus_cntl);
 
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        if (rdev->flags & RADEON_IS_PCIE)
 
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                WREG32(RV370_BUS_CNTL, bus_cntl);
 
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        else
 
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                WREG32(RADEON_BUS_CNTL, bus_cntl);
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        WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
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        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
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                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);