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Viewing changes to drivers/net/wireless/iwlwifi/iwl-eeprom.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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drivers/net/wireless/iwlwifi/iwl-eeprom.c
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 *
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 * GPL LICENSE SUMMARY
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 *
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 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
 
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 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of version 2 of the GNU General Public License as
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 *
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 * BSD LICENSE
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 *
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 * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
 
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 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
142
142
 *
143
143
******************************************************************************/
144
144
 
 
145
/*
 
146
 * The device's EEPROM semaphore prevents conflicts between driver and uCode
 
147
 * when accessing the EEPROM; each access is a series of pulses to/from the
 
148
 * EEPROM chip, not a single event, so even reads could conflict if they
 
149
 * weren't arbitrated by the semaphore.
 
150
 */
 
151
static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
 
152
{
 
153
        u16 count;
 
154
        int ret;
 
155
 
 
156
        for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
 
157
                /* Request semaphore */
 
158
                iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 
159
                            CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 
160
 
 
161
                /* See if we got it */
 
162
                ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
 
163
                                CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 
164
                                CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 
165
                                EEPROM_SEM_TIMEOUT);
 
166
                if (ret >= 0) {
 
167
                        IWL_DEBUG_EEPROM(priv,
 
168
                                "Acquired semaphore after %d tries.\n",
 
169
                                count+1);
 
170
                        return ret;
 
171
                }
 
172
        }
 
173
 
 
174
        return ret;
 
175
}
 
176
 
 
177
static void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
 
178
{
 
179
        iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
 
180
                CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 
181
 
 
182
}
 
183
 
145
184
static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
146
185
{
147
186
        u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
177
216
 
178
217
static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
179
218
{
180
 
        u32 otpgp;
 
219
        iwl_read32(priv, CSR_OTP_GP_REG);
181
220
 
182
 
        otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
183
221
        if (mode == IWL_OTP_ACCESS_ABSOLUTE)
184
222
                iwl_clear_bit(priv, CSR_OTP_GP_REG,
185
 
                                CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 
223
                              CSR_OTP_GP_REG_OTP_ACCESS_MODE);
186
224
        else
187
225
                iwl_set_bit(priv, CSR_OTP_GP_REG,
188
 
                                CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 
226
                            CSR_OTP_GP_REG_OTP_ACCESS_MODE);
189
227
}
190
228
 
191
 
static int iwlcore_get_nvm_type(struct iwl_priv *priv)
 
229
static int iwlcore_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
192
230
{
193
231
        u32 otpgp;
194
232
        int nvm_type;
195
233
 
196
234
        /* OTP only valid for CP/PP and after */
197
 
        switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 
235
        switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
198
236
        case CSR_HW_REV_TYPE_NONE:
199
237
                IWL_ERR(priv, "Unknown hardware type\n");
200
238
                return -ENOENT;
201
 
        case CSR_HW_REV_TYPE_3945:
202
 
        case CSR_HW_REV_TYPE_4965:
203
239
        case CSR_HW_REV_TYPE_5300:
204
240
        case CSR_HW_REV_TYPE_5350:
205
241
        case CSR_HW_REV_TYPE_5100:
217
253
        return  nvm_type;
218
254
}
219
255
 
220
 
const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
221
 
{
222
 
        BUG_ON(offset >= priv->cfg->base_params->eeprom_size);
223
 
        return &priv->eeprom[offset];
224
 
}
225
 
EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
226
 
 
227
256
static int iwl_init_otp_access(struct iwl_priv *priv)
228
257
{
229
258
        int ret;
230
259
 
231
260
        /* Enable 40MHz radio clock */
232
 
        _iwl_write32(priv, CSR_GP_CNTRL,
233
 
                     _iwl_read32(priv, CSR_GP_CNTRL) |
234
 
                     CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 
261
        iwl_write32(priv, CSR_GP_CNTRL,
 
262
                    iwl_read32(priv, CSR_GP_CNTRL) |
 
263
                    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
235
264
 
236
265
        /* wait for clock to be ready */
237
266
        ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
238
 
                                  CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
239
 
                                  CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
240
 
                                  25000);
 
267
                                 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 
268
                                 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 
269
                                 25000);
241
270
        if (ret < 0)
242
271
                IWL_ERR(priv, "Time out access OTP\n");
243
272
        else {
264
293
        u32 r;
265
294
        u32 otpgp;
266
295
 
267
 
        _iwl_write32(priv, CSR_EEPROM_REG,
268
 
                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 
296
        iwl_write32(priv, CSR_EEPROM_REG,
 
297
                    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
269
298
        ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
270
 
                                  CSR_EEPROM_REG_READ_VALID_MSK,
271
 
                                  CSR_EEPROM_REG_READ_VALID_MSK,
272
 
                                  IWL_EEPROM_ACCESS_TIMEOUT);
 
299
                                 CSR_EEPROM_REG_READ_VALID_MSK,
 
300
                                 CSR_EEPROM_REG_READ_VALID_MSK,
 
301
                                 IWL_EEPROM_ACCESS_TIMEOUT);
273
302
        if (ret < 0) {
274
303
                IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
275
304
                return ret;
276
305
        }
277
 
        r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 
306
        r = iwl_read32(priv, CSR_EEPROM_REG);
278
307
        /* check for ECC errors: */
279
308
        otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
280
309
        if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
382
411
{
383
412
        return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
384
413
}
385
 
EXPORT_SYMBOL(iwl_eeprom_query_addr);
386
414
 
387
415
u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
388
416
{
390
418
                return 0;
391
419
        return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
392
420
}
393
 
EXPORT_SYMBOL(iwl_eeprom_query16);
394
421
 
395
422
/**
396
423
 * iwl_eeprom_init - read EEPROM contents
399
426
 *
400
427
 * NOTE:  This routine uses the non-debug IO access functions.
401
428
 */
402
 
int iwl_eeprom_init(struct iwl_priv *priv)
 
429
int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
403
430
{
404
431
        __le16 *e;
405
432
        u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
409
436
        u16 validblockaddr = 0;
410
437
        u16 cache_addr = 0;
411
438
 
412
 
        priv->nvm_device_type = iwlcore_get_nvm_type(priv);
 
439
        priv->nvm_device_type = iwlcore_get_nvm_type(priv, hw_rev);
413
440
        if (priv->nvm_device_type == -ENOENT)
414
441
                return -ENOENT;
415
442
        /* allocate eeprom */
432
459
        }
433
460
 
434
461
        /* Make sure driver (instead of uCode) is allowed to read EEPROM */
435
 
        ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
 
462
        ret = iwl_eeprom_acquire_semaphore(priv);
436
463
        if (ret < 0) {
437
464
                IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
438
465
                ret = -ENOENT;
447
474
                        ret = -ENOENT;
448
475
                        goto done;
449
476
                }
450
 
                _iwl_write32(priv, CSR_EEPROM_GP,
451
 
                             iwl_read32(priv, CSR_EEPROM_GP) &
452
 
                             ~CSR_EEPROM_GP_IF_OWNER_MSK);
 
477
                iwl_write32(priv, CSR_EEPROM_GP,
 
478
                            iwl_read32(priv, CSR_EEPROM_GP) &
 
479
                            ~CSR_EEPROM_GP_IF_OWNER_MSK);
453
480
 
454
481
                iwl_set_bit(priv, CSR_OTP_GP_REG,
455
482
                             CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
476
503
                for (addr = 0; addr < sz; addr += sizeof(u16)) {
477
504
                        u32 r;
478
505
 
479
 
                        _iwl_write32(priv, CSR_EEPROM_REG,
480
 
                                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 
506
                        iwl_write32(priv, CSR_EEPROM_REG,
 
507
                                    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
481
508
 
482
509
                        ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
483
510
                                                  CSR_EEPROM_REG_READ_VALID_MSK,
487
514
                                IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
488
515
                                goto done;
489
516
                        }
490
 
                        r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 
517
                        r = iwl_read32(priv, CSR_EEPROM_REG);
491
518
                        e[addr / 2] = cpu_to_le16(r >> 16);
492
519
                }
493
520
        }
499
526
 
500
527
        ret = 0;
501
528
done:
502
 
        priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
 
529
        iwl_eeprom_release_semaphore(priv);
503
530
 
504
531
err:
505
532
        if (ret)
509
536
alloc_err:
510
537
        return ret;
511
538
}
512
 
EXPORT_SYMBOL(iwl_eeprom_init);
513
539
 
514
540
void iwl_eeprom_free(struct iwl_priv *priv)
515
541
{
516
542
        kfree(priv->eeprom);
517
543
        priv->eeprom = NULL;
518
544
}
519
 
EXPORT_SYMBOL(iwl_eeprom_free);
520
545
 
521
546
static void iwl_init_band_reference(const struct iwl_priv *priv,
522
547
                        int eep_band, int *eeprom_ch_count,
724
749
                                             flags & EEPROM_CHANNEL_RADAR))
725
750
                                       ? "" : "not ");
726
751
 
727
 
                        /* Set the tx_power_user_lmt to the highest power
728
 
                         * supported by any channel */
729
 
                        if (eeprom_ch_info[ch].max_power_avg >
730
 
                                                priv->tx_power_user_lmt)
731
 
                                priv->tx_power_user_lmt =
732
 
                                    eeprom_ch_info[ch].max_power_avg;
733
 
 
734
752
                        ch_info++;
735
753
                }
736
754
        }
779
797
 
780
798
        return 0;
781
799
}
782
 
EXPORT_SYMBOL(iwl_init_channel_map);
783
800
 
784
801
/*
785
802
 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
789
806
        kfree(priv->channel_info);
790
807
        priv->channel_count = 0;
791
808
}
792
 
EXPORT_SYMBOL(iwl_free_channel_map);
793
809
 
794
810
/**
795
811
 * iwl_get_channel_info - Find driver's private channel info
818
834
 
819
835
        return NULL;
820
836
}
821
 
EXPORT_SYMBOL(iwl_get_channel_info);