44
44
#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
46
static void intc_irq_unmask(unsigned int irq)
48
writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
51
static void intc_irq_mask(unsigned int irq)
53
writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
56
static int intc_irq_set_wake(unsigned int irq, unsigned int on)
46
static inline unsigned long intc_irq_bit(struct irq_data *data)
48
return (unsigned long)irq_data_get_irq_chip_data(data);
51
static void intc_irq_unmask(struct irq_data *data)
53
writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
56
static void intc_irq_mask(struct irq_data *data)
58
writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
61
static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
59
jz_intc_wakeup |= IRQ_BIT(irq);
64
jz_intc_wakeup |= intc_irq_bit(data);
61
jz_intc_wakeup &= ~IRQ_BIT(irq);
66
jz_intc_wakeup &= ~intc_irq_bit(data);
66
71
static struct irq_chip intc_irq_type = {
68
.mask = intc_irq_mask,
69
.mask_ack = intc_irq_mask,
70
.unmask = intc_irq_unmask,
71
.set_wake = intc_irq_set_wake,
73
.irq_mask = intc_irq_mask,
74
.irq_mask_ack = intc_irq_mask,
75
.irq_unmask = intc_irq_unmask,
76
.irq_set_wake = intc_irq_set_wake,
74
79
static irqreturn_t jz4740_cascade(int irq, void *data)
96
101
jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
104
writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
98
106
for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
100
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
107
irq_set_chip_data(i, (void *)IRQ_BIT(i));
108
irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
103
111
setup_irq(2, &jz4740_cascade_action);