97
97
iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
99
99
/* This will initialize clock framework */
103
103
/* pad multiplexing support */
105
struct pmx_dev_mode pmx_firda_modes[] = {
105
static struct pmx_dev_mode pmx_firda_modes[] = {
107
107
.ids = 0xffffffff,
108
108
.mask = PMX_FIRDA_MASK,
112
struct pmx_dev pmx_firda = {
112
struct pmx_dev spear3xx_pmx_firda = {
114
114
.modes = pmx_firda_modes,
115
115
.mode_count = ARRAY_SIZE(pmx_firda_modes),
116
116
.enb_on_reset = 0,
119
struct pmx_dev_mode pmx_i2c_modes[] = {
119
static struct pmx_dev_mode pmx_i2c_modes[] = {
121
121
.ids = 0xffffffff,
122
122
.mask = PMX_I2C_MASK,
126
struct pmx_dev pmx_i2c = {
126
struct pmx_dev spear3xx_pmx_i2c = {
128
128
.modes = pmx_i2c_modes,
129
129
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
130
130
.enb_on_reset = 0,
133
struct pmx_dev_mode pmx_ssp_cs_modes[] = {
133
static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
135
135
.ids = 0xffffffff,
136
136
.mask = PMX_SSP_CS_MASK,
140
struct pmx_dev pmx_ssp_cs = {
140
struct pmx_dev spear3xx_pmx_ssp_cs = {
141
141
.name = "ssp_chip_selects",
142
142
.modes = pmx_ssp_cs_modes,
143
143
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
144
144
.enb_on_reset = 0,
147
struct pmx_dev_mode pmx_ssp_modes[] = {
147
static struct pmx_dev_mode pmx_ssp_modes[] = {
149
149
.ids = 0xffffffff,
150
150
.mask = PMX_SSP_MASK,
154
struct pmx_dev pmx_ssp = {
154
struct pmx_dev spear3xx_pmx_ssp = {
156
156
.modes = pmx_ssp_modes,
157
157
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
158
158
.enb_on_reset = 0,
161
struct pmx_dev_mode pmx_mii_modes[] = {
161
static struct pmx_dev_mode pmx_mii_modes[] = {
163
163
.ids = 0xffffffff,
164
164
.mask = PMX_MII_MASK,
168
struct pmx_dev pmx_mii = {
168
struct pmx_dev spear3xx_pmx_mii = {
170
170
.modes = pmx_mii_modes,
171
171
.mode_count = ARRAY_SIZE(pmx_mii_modes),
172
172
.enb_on_reset = 0,
175
struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
175
static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
177
177
.ids = 0xffffffff,
178
178
.mask = PMX_GPIO_PIN0_MASK,
182
struct pmx_dev pmx_gpio_pin0 = {
182
struct pmx_dev spear3xx_pmx_gpio_pin0 = {
183
183
.name = "gpio_pin0",
184
184
.modes = pmx_gpio_pin0_modes,
185
185
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
186
186
.enb_on_reset = 0,
189
struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
189
static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
191
191
.ids = 0xffffffff,
192
192
.mask = PMX_GPIO_PIN1_MASK,
196
struct pmx_dev pmx_gpio_pin1 = {
196
struct pmx_dev spear3xx_pmx_gpio_pin1 = {
197
197
.name = "gpio_pin1",
198
198
.modes = pmx_gpio_pin1_modes,
199
199
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
200
200
.enb_on_reset = 0,
203
struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
203
static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
205
205
.ids = 0xffffffff,
206
206
.mask = PMX_GPIO_PIN2_MASK,
210
struct pmx_dev pmx_gpio_pin2 = {
210
struct pmx_dev spear3xx_pmx_gpio_pin2 = {
211
211
.name = "gpio_pin2",
212
212
.modes = pmx_gpio_pin2_modes,
213
213
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
214
214
.enb_on_reset = 0,
217
struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
217
static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
219
219
.ids = 0xffffffff,
220
220
.mask = PMX_GPIO_PIN3_MASK,
224
struct pmx_dev pmx_gpio_pin3 = {
224
struct pmx_dev spear3xx_pmx_gpio_pin3 = {
225
225
.name = "gpio_pin3",
226
226
.modes = pmx_gpio_pin3_modes,
227
227
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
228
228
.enb_on_reset = 0,
231
struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
231
static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
233
233
.ids = 0xffffffff,
234
234
.mask = PMX_GPIO_PIN4_MASK,
238
struct pmx_dev pmx_gpio_pin4 = {
238
struct pmx_dev spear3xx_pmx_gpio_pin4 = {
239
239
.name = "gpio_pin4",
240
240
.modes = pmx_gpio_pin4_modes,
241
241
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
242
242
.enb_on_reset = 0,
245
struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
245
static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
247
247
.ids = 0xffffffff,
248
248
.mask = PMX_GPIO_PIN5_MASK,
252
struct pmx_dev pmx_gpio_pin5 = {
252
struct pmx_dev spear3xx_pmx_gpio_pin5 = {
253
253
.name = "gpio_pin5",
254
254
.modes = pmx_gpio_pin5_modes,
255
255
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
256
256
.enb_on_reset = 0,
259
struct pmx_dev_mode pmx_uart0_modem_modes[] = {
259
static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
261
261
.ids = 0xffffffff,
262
262
.mask = PMX_UART0_MODEM_MASK,
266
struct pmx_dev pmx_uart0_modem = {
266
struct pmx_dev spear3xx_pmx_uart0_modem = {
267
267
.name = "uart0_modem",
268
268
.modes = pmx_uart0_modem_modes,
269
269
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
270
270
.enb_on_reset = 0,
273
struct pmx_dev_mode pmx_uart0_modes[] = {
273
static struct pmx_dev_mode pmx_uart0_modes[] = {
275
275
.ids = 0xffffffff,
276
276
.mask = PMX_UART0_MASK,
280
struct pmx_dev pmx_uart0 = {
280
struct pmx_dev spear3xx_pmx_uart0 = {
282
282
.modes = pmx_uart0_modes,
283
283
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
284
284
.enb_on_reset = 0,
287
struct pmx_dev_mode pmx_timer_3_4_modes[] = {
287
static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
289
289
.ids = 0xffffffff,
290
290
.mask = PMX_TIMER_3_4_MASK,
294
struct pmx_dev pmx_timer_3_4 = {
294
struct pmx_dev spear3xx_pmx_timer_3_4 = {
295
295
.name = "timer_3_4",
296
296
.modes = pmx_timer_3_4_modes,
297
297
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
298
298
.enb_on_reset = 0,
301
struct pmx_dev_mode pmx_timer_1_2_modes[] = {
301
static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
303
303
.ids = 0xffffffff,
304
304
.mask = PMX_TIMER_1_2_MASK,
308
struct pmx_dev pmx_timer_1_2 = {
308
struct pmx_dev spear3xx_pmx_timer_1_2 = {
309
309
.name = "timer_1_2",
310
310
.modes = pmx_timer_1_2_modes,
311
311
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
315
315
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
316
316
/* plgpios devices */
317
struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
317
static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
320
320
.mask = PMX_FIRDA_MASK,
324
struct pmx_dev pmx_plgpio_0_1 = {
324
struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
325
325
.name = "plgpio 0 and 1",
326
326
.modes = pmx_plgpio_0_1_modes,
327
327
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
328
328
.enb_on_reset = 1,
331
struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
331
static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
334
334
.mask = PMX_UART0_MASK,
338
struct pmx_dev pmx_plgpio_2_3 = {
338
struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
339
339
.name = "plgpio 2 and 3",
340
340
.modes = pmx_plgpio_2_3_modes,
341
341
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
342
342
.enb_on_reset = 1,
345
struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
345
static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
348
348
.mask = PMX_I2C_MASK,
352
struct pmx_dev pmx_plgpio_4_5 = {
352
struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
353
353
.name = "plgpio 4 and 5",
354
354
.modes = pmx_plgpio_4_5_modes,
355
355
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
356
356
.enb_on_reset = 1,
359
struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
359
static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
362
362
.mask = PMX_SSP_MASK,
366
struct pmx_dev pmx_plgpio_6_9 = {
366
struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
367
367
.name = "plgpio 6 to 9",
368
368
.modes = pmx_plgpio_6_9_modes,
369
369
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
370
370
.enb_on_reset = 1,
373
struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
373
static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
376
376
.mask = PMX_MII_MASK,
380
struct pmx_dev pmx_plgpio_10_27 = {
380
struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
381
381
.name = "plgpio 10 to 27",
382
382
.modes = pmx_plgpio_10_27_modes,
383
383
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
384
384
.enb_on_reset = 1,
387
struct pmx_dev_mode pmx_plgpio_28_modes[] = {
387
static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
390
390
.mask = PMX_GPIO_PIN0_MASK,
394
struct pmx_dev pmx_plgpio_28 = {
394
struct pmx_dev spear3xx_pmx_plgpio_28 = {
395
395
.name = "plgpio 28",
396
396
.modes = pmx_plgpio_28_modes,
397
397
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
398
398
.enb_on_reset = 1,
401
struct pmx_dev_mode pmx_plgpio_29_modes[] = {
401
static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
404
404
.mask = PMX_GPIO_PIN1_MASK,
408
struct pmx_dev pmx_plgpio_29 = {
408
struct pmx_dev spear3xx_pmx_plgpio_29 = {
409
409
.name = "plgpio 29",
410
410
.modes = pmx_plgpio_29_modes,
411
411
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
412
412
.enb_on_reset = 1,
415
struct pmx_dev_mode pmx_plgpio_30_modes[] = {
415
static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
418
418
.mask = PMX_GPIO_PIN2_MASK,
422
struct pmx_dev pmx_plgpio_30 = {
422
struct pmx_dev spear3xx_pmx_plgpio_30 = {
423
423
.name = "plgpio 30",
424
424
.modes = pmx_plgpio_30_modes,
425
425
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
426
426
.enb_on_reset = 1,
429
struct pmx_dev_mode pmx_plgpio_31_modes[] = {
429
static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
432
432
.mask = PMX_GPIO_PIN3_MASK,
436
struct pmx_dev pmx_plgpio_31 = {
436
struct pmx_dev spear3xx_pmx_plgpio_31 = {
437
437
.name = "plgpio 31",
438
438
.modes = pmx_plgpio_31_modes,
439
439
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
440
440
.enb_on_reset = 1,
443
struct pmx_dev_mode pmx_plgpio_32_modes[] = {
443
static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
446
446
.mask = PMX_GPIO_PIN4_MASK,
450
struct pmx_dev pmx_plgpio_32 = {
450
struct pmx_dev spear3xx_pmx_plgpio_32 = {
451
451
.name = "plgpio 32",
452
452
.modes = pmx_plgpio_32_modes,
453
453
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
454
454
.enb_on_reset = 1,
457
struct pmx_dev_mode pmx_plgpio_33_modes[] = {
457
static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
460
460
.mask = PMX_GPIO_PIN5_MASK,
464
struct pmx_dev pmx_plgpio_33 = {
464
struct pmx_dev spear3xx_pmx_plgpio_33 = {
465
465
.name = "plgpio 33",
466
466
.modes = pmx_plgpio_33_modes,
467
467
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
468
468
.enb_on_reset = 1,
471
struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
471
static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
474
474
.mask = PMX_SSP_CS_MASK,
478
struct pmx_dev pmx_plgpio_34_36 = {
478
struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
479
479
.name = "plgpio 34 to 36",
480
480
.modes = pmx_plgpio_34_36_modes,
481
481
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
482
482
.enb_on_reset = 1,
485
struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
485
static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
488
488
.mask = PMX_UART0_MODEM_MASK,
492
struct pmx_dev pmx_plgpio_37_42 = {
492
struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
493
493
.name = "plgpio 37 to 42",
494
494
.modes = pmx_plgpio_37_42_modes,
495
495
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
496
496
.enb_on_reset = 1,
499
struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
499
static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
502
502
.mask = PMX_TIMER_1_2_MASK,
506
struct pmx_dev pmx_plgpio_43_44_47_48 = {
506
struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
507
507
.name = "plgpio 43, 44, 47 and 48",
508
508
.modes = pmx_plgpio_43_44_47_48_modes,
509
509
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
510
510
.enb_on_reset = 1,
513
struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
513
static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
516
516
.mask = PMX_TIMER_3_4_MASK,
520
struct pmx_dev pmx_plgpio_45_46_49_50 = {
520
struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
521
521
.name = "plgpio 45, 46, 49 and 50",
522
522
.modes = pmx_plgpio_45_46_49_50_modes,
523
523
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),