200
200
/* Initialize global IRQ's, fast path */
201
201
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
202
set_irq_chip(irq, &h720x_global_chip);
203
set_irq_handler(irq, handle_level_irq);
202
irq_set_chip_and_handler(irq, &h720x_global_chip,
204
204
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
207
207
/* Initialize multiplexed IRQ's, slow path */
208
208
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
209
set_irq_chip(irq, &h720x_gpio_chip);
210
set_irq_handler(irq, handle_edge_irq);
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irq_set_chip_and_handler(irq, &h720x_gpio_chip,
211
211
set_irq_flags(irq, IRQF_VALID );
213
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
214
set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
215
set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
216
set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
213
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
214
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
215
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
216
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
218
218
#ifdef CONFIG_CPU_H7202
219
219
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
220
set_irq_chip(irq, &h720x_gpio_chip);
221
set_irq_handler(irq, handle_edge_irq);
220
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
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222
set_irq_flags(irq, IRQF_VALID );
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set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
224
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
227
227
/* Enable multiplexed irq's */