109
109
#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
111
111
/* INTC1 - interrupt controller 1 */
113
113
#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
115
115
#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
116
116
#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
117
117
/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */