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* Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
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* Copyright (C) 2011 Samsung Electronics Co., Ltd.
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* Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-subdev.h>
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#include <plat/mipi_csis.h>
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#include "mipi-csis.h"
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Debug level (0-1)");
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/* Register map definition */
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/* CSIS global control */
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#define S5PCSIS_CTRL 0x00
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#define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
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#define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
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#define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
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#define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
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#define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
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#define S5PCSIS_CTRL_RESET (1 << 4)
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#define S5PCSIS_CTRL_ENABLE (1 << 0)
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#define S5PCSIS_DPHYCTRL 0x04
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#define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
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#define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
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#define S5PCSIS_CONFIG 0x08
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#define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
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#define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
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#define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
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#define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
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/* User defined formats, x = 1...4 */
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#define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
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#define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
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#define S5PCSIS_CFG_NR_LANE_MASK 3
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#define S5PCSIS_INTMSK 0x10
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#define S5PCSIS_INTMSK_EN_ALL 0xf000003f
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#define S5PCSIS_INTSRC 0x14
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/* Pixel resolution */
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#define S5PCSIS_RESOL 0x2c
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#define CSIS_MAX_PIX_WIDTH 0xffff
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#define CSIS_MAX_PIX_HEIGHT 0xffff
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static char *csi_clock_name[] = {
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[CSIS_CLK_MUX] = "sclk_csis",
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[CSIS_CLK_GATE] = "csis",
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#define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
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* struct csis_state - the driver's internal state data structure
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* @lock: mutex serializing the subdev and power management operations,
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* protecting @format and @flags members
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* @pads: CSIS pads array
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* @sd: v4l2_subdev associated with CSIS device instance
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* @pdev: CSIS platform device
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* @regs_res: requested I/O register memory resource
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* @regs: mmaped I/O registers memory
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* @irq: requested s5p-mipi-csis irq number
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* @flags: the state variable for power and streaming control
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* @csis_fmt: current CSIS pixel format
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* @format: common media bus format for the source and sink pad
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struct media_pad pads[CSIS_PADS_NUM];
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struct v4l2_subdev sd;
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struct platform_device *pdev;
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struct resource *regs_res;
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struct clk *clock[NUM_CSIS_CLOCKS];
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struct regulator *supply;
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const struct csis_pix_format *csis_fmt;
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struct v4l2_mbus_framefmt format;
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* struct csis_pix_format - CSIS pixel format description
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* @pix_width_alignment: horizontal pixel alignment, width will be
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* multiple of 2^pix_width_alignment
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* @code: corresponding media bus code
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* @fmt_reg: S5PCSIS_CONFIG register value
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struct csis_pix_format {
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unsigned int pix_width_alignment;
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enum v4l2_mbus_pixelcode code;
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static const struct csis_pix_format s5pcsis_formats[] = {
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.code = V4L2_MBUS_FMT_VYUY8_2X8,
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.fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
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.code = V4L2_MBUS_FMT_JPEG_1X8,
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.fmt_reg = S5PCSIS_CFG_FMT_USER(1),
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#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
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#define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
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static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
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return container_of(sdev, struct csis_state, sd);
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static const struct csis_pix_format *find_csis_format(
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struct v4l2_mbus_framefmt *mf)
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for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
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if (mf->code == s5pcsis_formats[i].code)
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return &s5pcsis_formats[i];
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static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
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u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
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val = on ? val | S5PCSIS_INTMSK_EN_ALL :
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val & ~S5PCSIS_INTMSK_EN_ALL;
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s5pcsis_write(state, S5PCSIS_INTMSK, val);
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static void s5pcsis_reset(struct csis_state *state)
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u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
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s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
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static void s5pcsis_system_enable(struct csis_state *state, int on)
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val = s5pcsis_read(state, S5PCSIS_CTRL);
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val |= S5PCSIS_CTRL_ENABLE;
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val &= ~S5PCSIS_CTRL_ENABLE;
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s5pcsis_write(state, S5PCSIS_CTRL, val);
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val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
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val |= S5PCSIS_DPHYCTRL_ENABLE;
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val &= ~S5PCSIS_DPHYCTRL_ENABLE;
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s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
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/* Called with the state.lock mutex held */
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static void __s5pcsis_set_format(struct csis_state *state)
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struct v4l2_mbus_framefmt *mf = &state->format;
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v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
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mf->code, mf->width, mf->height);
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val = s5pcsis_read(state, S5PCSIS_CONFIG);
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val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
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s5pcsis_write(state, S5PCSIS_CONFIG, val);
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/* Pixel resolution */
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val = (mf->width << 16) | mf->height;
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s5pcsis_write(state, S5PCSIS_RESOL, val);
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static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
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u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
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val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
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s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
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static void s5pcsis_set_params(struct csis_state *state)
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struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
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val = s5pcsis_read(state, S5PCSIS_CONFIG);
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val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
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s5pcsis_write(state, S5PCSIS_CONFIG, val);
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__s5pcsis_set_format(state);
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s5pcsis_set_hsync_settle(state, pdata->hs_settle);
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val = s5pcsis_read(state, S5PCSIS_CTRL);
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if (pdata->alignment == 32)
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val |= S5PCSIS_CTRL_ALIGN_32BIT;
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val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
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/* Not using external clock. */
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val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
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s5pcsis_write(state, S5PCSIS_CTRL, val);
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/* Update the shadow register. */
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val = s5pcsis_read(state, S5PCSIS_CTRL);
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s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
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static void s5pcsis_clk_put(struct csis_state *state)
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for (i = 0; i < NUM_CSIS_CLOCKS; i++)
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if (!IS_ERR_OR_NULL(state->clock[i]))
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clk_put(state->clock[i]);
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static int s5pcsis_clk_get(struct csis_state *state)
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struct device *dev = &state->pdev->dev;
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for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
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state->clock[i] = clk_get(dev, csi_clock_name[i]);
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if (IS_ERR(state->clock[i])) {
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s5pcsis_clk_put(state);
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dev_err(dev, "failed to get clock: %s\n",
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static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
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struct csis_state *state = sd_to_csis_state(sd);
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struct device *dev = &state->pdev->dev;
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return pm_runtime_get_sync(dev);
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return pm_runtime_put_sync(dev);
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static void s5pcsis_start_stream(struct csis_state *state)
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s5pcsis_reset(state);
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s5pcsis_set_params(state);
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s5pcsis_system_enable(state, true);
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s5pcsis_enable_interrupts(state, true);
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static void s5pcsis_stop_stream(struct csis_state *state)
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s5pcsis_enable_interrupts(state, false);
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s5pcsis_system_enable(state, false);
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/* v4l2_subdev operations */
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static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
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struct csis_state *state = sd_to_csis_state(sd);
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v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
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__func__, enable, state->flags);
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ret = pm_runtime_get_sync(&state->pdev->dev);
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mutex_lock(&state->lock);
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if (state->flags & ST_SUSPENDED) {
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s5pcsis_start_stream(state);
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state->flags |= ST_STREAMING;
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s5pcsis_stop_stream(state);
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state->flags &= ~ST_STREAMING;
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mutex_unlock(&state->lock);
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pm_runtime_put(&state->pdev->dev);
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return ret == 1 ? 0 : ret;
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static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
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struct v4l2_subdev_fh *fh,
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struct v4l2_subdev_mbus_code_enum *code)
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if (code->index >= ARRAY_SIZE(s5pcsis_formats))
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code->code = s5pcsis_formats[code->index].code;
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static struct csis_pix_format const *s5pcsis_try_format(
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struct v4l2_mbus_framefmt *mf)
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struct csis_pix_format const *csis_fmt;
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csis_fmt = find_csis_format(mf);
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if (csis_fmt == NULL)
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csis_fmt = &s5pcsis_formats[0];
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mf->code = csis_fmt->code;
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v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
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csis_fmt->pix_width_alignment,
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&mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
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static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
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struct csis_state *state, struct v4l2_subdev_fh *fh,
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u32 pad, enum v4l2_subdev_format_whence which)
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if (which == V4L2_SUBDEV_FORMAT_TRY)
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return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
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return &state->format;
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static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
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struct v4l2_subdev_format *fmt)
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struct csis_state *state = sd_to_csis_state(sd);
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struct csis_pix_format const *csis_fmt;
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struct v4l2_mbus_framefmt *mf;
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if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
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mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
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if (fmt->pad == CSIS_PAD_SOURCE) {
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mutex_lock(&state->lock);
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mutex_unlock(&state->lock);
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csis_fmt = s5pcsis_try_format(&fmt->format);
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mutex_lock(&state->lock);
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if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
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state->csis_fmt = csis_fmt;
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mutex_unlock(&state->lock);
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static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
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struct v4l2_subdev_format *fmt)
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struct csis_state *state = sd_to_csis_state(sd);
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struct v4l2_mbus_framefmt *mf;
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if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
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mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
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mutex_lock(&state->lock);
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mutex_unlock(&state->lock);
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static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
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.s_power = s5pcsis_s_power,
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static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
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.enum_mbus_code = s5pcsis_enum_mbus_code,
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.get_fmt = s5pcsis_get_fmt,
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.set_fmt = s5pcsis_set_fmt,
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static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
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.s_stream = s5pcsis_s_stream,
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static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
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.core = &s5pcsis_core_ops,
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.pad = &s5pcsis_pad_ops,
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.video = &s5pcsis_video_ops,
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static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
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struct csis_state *state = dev_id;
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/* Just clear the interrupt pending bits. */
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val = s5pcsis_read(state, S5PCSIS_INTSRC);
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s5pcsis_write(state, S5PCSIS_INTSRC, val);
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static int __devinit s5pcsis_probe(struct platform_device *pdev)
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struct s5p_platform_mipi_csis *pdata;
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struct resource *mem_res;
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struct resource *regs_res;
461
struct csis_state *state;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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mutex_init(&state->lock);
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pdata = pdev->dev.platform_data;
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if (pdata == NULL || pdata->phy_enable == NULL) {
473
dev_err(&pdev->dev, "Platform data not fully specified\n");
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if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
478
pdata->lanes > CSIS0_MAX_LANES) {
480
dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
485
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487
dev_err(&pdev->dev, "Failed to get IO memory region\n");
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regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
494
dev_err(&pdev->dev, "Failed to request IO memory region\n");
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state->regs_res = regs_res;
499
state->regs = ioremap(mem_res->start, resource_size(mem_res));
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dev_err(&pdev->dev, "Failed to remap IO region\n");
505
ret = s5pcsis_clk_get(state);
509
clk_enable(state->clock[CSIS_CLK_MUX]);
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clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
513
dev_WARN(&pdev->dev, "No clock frequency specified!\n");
515
state->irq = platform_get_irq(pdev, 0);
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if (state->irq < 0) {
518
dev_err(&pdev->dev, "Failed to get irq\n");
522
if (!pdata->fixed_phy_vdd) {
523
state->supply = regulator_get(&pdev->dev, "vdd");
524
if (IS_ERR(state->supply)) {
525
ret = PTR_ERR(state->supply);
526
state->supply = NULL;
531
ret = request_irq(state->irq, s5pcsis_irq_handler, 0,
532
dev_name(&pdev->dev), state);
534
dev_err(&pdev->dev, "request_irq failed\n");
538
v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
539
state->sd.owner = THIS_MODULE;
540
strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name));
541
state->csis_fmt = &s5pcsis_formats[0];
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state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
544
state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
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ret = media_entity_init(&state->sd.entity,
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CSIS_PADS_NUM, state->pads, 0);
550
/* This allows to retrieve the platform device id by the host driver */
551
v4l2_set_subdevdata(&state->sd, pdev);
553
/* .. and a pointer to the subdev. */
554
platform_set_drvdata(pdev, &state->sd);
556
state->flags = ST_SUSPENDED;
557
pm_runtime_enable(&pdev->dev);
562
free_irq(state->irq, state);
565
regulator_put(state->supply);
567
clk_disable(state->clock[CSIS_CLK_MUX]);
568
s5pcsis_clk_put(state);
570
iounmap(state->regs);
572
release_mem_region(regs_res->start, resource_size(regs_res));
578
static int s5pcsis_suspend(struct device *dev)
580
struct s5p_platform_mipi_csis *pdata = dev->platform_data;
581
struct platform_device *pdev = to_platform_device(dev);
582
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
583
struct csis_state *state = sd_to_csis_state(sd);
586
v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
587
__func__, state->flags);
589
mutex_lock(&state->lock);
590
if (state->flags & ST_POWERED) {
591
s5pcsis_stop_stream(state);
592
ret = pdata->phy_enable(state->pdev, false);
596
ret = regulator_disable(state->supply);
600
clk_disable(state->clock[CSIS_CLK_GATE]);
601
state->flags &= ~ST_POWERED;
603
state->flags |= ST_SUSPENDED;
605
mutex_unlock(&state->lock);
606
return ret ? -EAGAIN : 0;
609
static int s5pcsis_resume(struct device *dev)
611
struct s5p_platform_mipi_csis *pdata = dev->platform_data;
612
struct platform_device *pdev = to_platform_device(dev);
613
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
614
struct csis_state *state = sd_to_csis_state(sd);
617
v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
618
__func__, state->flags);
620
mutex_lock(&state->lock);
621
if (!(state->flags & ST_SUSPENDED))
624
if (!(state->flags & ST_POWERED)) {
626
ret = regulator_enable(state->supply);
630
ret = pdata->phy_enable(state->pdev, true);
632
state->flags |= ST_POWERED;
633
} else if (state->supply) {
634
regulator_disable(state->supply);
637
clk_enable(state->clock[CSIS_CLK_GATE]);
639
if (state->flags & ST_STREAMING)
640
s5pcsis_start_stream(state);
642
state->flags &= ~ST_SUSPENDED;
644
mutex_unlock(&state->lock);
645
return ret ? -EAGAIN : 0;
648
#ifdef CONFIG_PM_SLEEP
649
static int s5pcsis_pm_suspend(struct device *dev)
651
return s5pcsis_suspend(dev);
654
static int s5pcsis_pm_resume(struct device *dev)
658
ret = s5pcsis_resume(dev);
661
pm_runtime_disable(dev);
662
ret = pm_runtime_set_active(dev);
663
pm_runtime_enable(dev);
670
static int __devexit s5pcsis_remove(struct platform_device *pdev)
672
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
673
struct csis_state *state = sd_to_csis_state(sd);
674
struct resource *res = state->regs_res;
676
pm_runtime_disable(&pdev->dev);
677
s5pcsis_suspend(&pdev->dev);
678
clk_disable(state->clock[CSIS_CLK_MUX]);
679
pm_runtime_set_suspended(&pdev->dev);
681
s5pcsis_clk_put(state);
683
regulator_put(state->supply);
685
media_entity_cleanup(&state->sd.entity);
686
free_irq(state->irq, state);
687
iounmap(state->regs);
688
release_mem_region(res->start, resource_size(res));
694
static const struct dev_pm_ops s5pcsis_pm_ops = {
695
SET_RUNTIME_PM_OPS(s5pcsis_suspend, s5pcsis_resume, NULL)
696
SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_pm_suspend, s5pcsis_pm_resume)
699
static struct platform_driver s5pcsis_driver = {
700
.probe = s5pcsis_probe,
701
.remove = __devexit_p(s5pcsis_remove),
703
.name = CSIS_DRIVER_NAME,
704
.owner = THIS_MODULE,
705
.pm = &s5pcsis_pm_ops,
709
static int __init s5pcsis_init(void)
711
return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe);
714
static void __exit s5pcsis_exit(void)
716
platform_driver_unregister(&s5pcsis_driver);
719
module_init(s5pcsis_init);
720
module_exit(s5pcsis_exit);
722
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
723
MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver");
724
MODULE_LICENSE("GPL");