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Viewing changes to drivers/gpu/drm/i915/i915_gem_gtt.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/gpu/drm/i915/i915_gem_gtt.c
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#include "i915_trace.h"
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#include "intel_drv.h"
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/* XXX kill agp_type! */
 
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static unsigned int cache_level_to_agp_type(struct drm_device *dev,
 
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                                            enum i915_cache_level cache_level)
 
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{
 
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        switch (cache_level) {
 
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        case I915_CACHE_LLC_MLC:
 
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                if (INTEL_INFO(dev)->gen >= 6)
 
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                        return AGP_USER_CACHED_MEMORY_LLC_MLC;
 
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                /* Older chipsets do not have this extra level of CPU
 
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                 * cacheing, so fallthrough and request the PTE simply
 
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                 * as cached.
 
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                 */
 
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        case I915_CACHE_LLC:
 
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                return AGP_USER_CACHED_MEMORY;
 
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        default:
 
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        case I915_CACHE_NONE:
 
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                return AGP_USER_MEMORY;
 
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        }
 
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}
 
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void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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{
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        struct drm_i915_private *dev_priv = dev->dev_private;
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                              (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
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        list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 
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                unsigned int agp_type =
 
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                        cache_level_to_agp_type(dev, obj->cache_level);
 
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                i915_gem_clflush_object(obj);
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                if (dev_priv->mm.gtt->needs_dmar) {
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                        intel_gtt_insert_sg_entries(obj->sg_list,
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                                                    obj->num_sg,
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                                                    obj->gtt_space->start
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                                                        >> PAGE_SHIFT,
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                                                    obj->agp_type);
 
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                                                    obj->gtt_space->start >> PAGE_SHIFT,
 
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                                                    agp_type);
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                } else
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                        intel_gtt_insert_pages(obj->gtt_space->start
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                                                   >> PAGE_SHIFT,
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                                               obj->base.size >> PAGE_SHIFT,
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                                               obj->pages,
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                                               obj->agp_type);
 
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                                               agp_type);
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        }
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        intel_gtt_chipset_flush();
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{
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        struct drm_device *dev = obj->base.dev;
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        struct drm_i915_private *dev_priv = dev->dev_private;
 
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        unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
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        int ret;
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        if (dev_priv->mm.gtt->needs_dmar) {
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                intel_gtt_insert_sg_entries(obj->sg_list,
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                                            obj->num_sg,
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                                            obj->gtt_space->start >> PAGE_SHIFT,
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                                            obj->agp_type);
 
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                                            agp_type);
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        } else
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                intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
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                                       obj->base.size >> PAGE_SHIFT,
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                                       obj->pages,
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                                       obj->agp_type);
 
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                                       agp_type);
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        return 0;
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}