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#include <linux/signal.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/sysdev.h>
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#include <linux/syscore_ops.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <linux/module.h>
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static void pmac_mask_and_ack_irq(unsigned int virq)
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static void pmac_mask_and_ack_irq(struct irq_data *d)
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unsigned int src = irq_map[virq].hwirq;
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unsigned int src = irqd_to_hwirq(d);
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unsigned long bit = 1UL << (src & 0x1f);
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unsigned long flags;
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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static void pmac_ack_irq(unsigned int virq)
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static void pmac_ack_irq(struct irq_data *d)
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unsigned int src = irq_map[virq].hwirq;
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unsigned int src = irqd_to_hwirq(d);
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unsigned long bit = 1UL << (src & 0x1f);
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int i = src >> 5;
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unsigned long flags;
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/* When an irq gets requested for the first client, if it's an
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* edge interrupt, we clear any previous one on the controller
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static unsigned int pmac_startup_irq(unsigned int virq)
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static unsigned int pmac_startup_irq(struct irq_data *d)
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unsigned long flags;
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unsigned int src = irq_map[virq].hwirq;
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unsigned int src = irqd_to_hwirq(d);
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unsigned long bit = 1UL << (src & 0x1f);
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int i = src >> 5;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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if ((irq_to_desc(virq)->status & IRQ_LEVEL) == 0)
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if (!irqd_is_level_type(d))
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out_le32(&pmac_irq_hw[i]->ack, bit);
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__set_bit(src, ppc_cached_irq_mask);
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__pmac_set_irq_mask(src, 0);
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static void pmac_mask_irq(unsigned int virq)
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static void pmac_mask_irq(struct irq_data *d)
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unsigned long flags;
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unsigned int src = irq_map[virq].hwirq;
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unsigned int src = irqd_to_hwirq(d);
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__clear_bit(src, ppc_cached_irq_mask);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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static void pmac_unmask_irq(unsigned int virq)
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static void pmac_unmask_irq(struct irq_data *d)
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unsigned long flags;
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unsigned int src = irq_map[virq].hwirq;
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unsigned int src = irqd_to_hwirq(d);
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__set_bit(src, ppc_cached_irq_mask);
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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static int pmac_retrigger(unsigned int virq)
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static int pmac_retrigger(struct irq_data *d)
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unsigned long flags;
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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__pmac_retrigger(irq_map[virq].hwirq);
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__pmac_retrigger(irqd_to_hwirq(d));
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raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
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static struct irq_chip pmac_pic = {
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.name = "PMAC-PIC",
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.startup = pmac_startup_irq,
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.mask = pmac_mask_irq,
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.mask_ack = pmac_mask_and_ack_irq,
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.unmask = pmac_unmask_irq,
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.retrigger = pmac_retrigger,
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.irq_startup = pmac_startup_irq,
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.irq_mask = pmac_mask_irq,
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.irq_ack = pmac_ack_irq,
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.irq_mask_ack = pmac_mask_and_ack_irq,
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.irq_unmask = pmac_unmask_irq,
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.irq_retrigger = pmac_retrigger,
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static irqreturn_t gatwick_action(int cpl, void *dev_id)
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unsigned long bits = 0;
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unsigned long flags;
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void psurge_smp_message_recv(void);
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/* IPI's are a hack on the powersurge -- Cort */
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if ( smp_processor_id() != 0 ) {
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psurge_smp_message_recv();
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return NO_IRQ_IGNORE; /* ignore, already handled */
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#ifdef CONFIG_PPC_PMAC32_PSURGE
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/* IPI's are a hack on the powersurge -- Cort */
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if (smp_processor_id() != 0) {
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return psurge_secondary_virq;
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_PPC_PMAC32_PSURGE */
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raw_spin_lock_irqsave(&pmac_pic_lock, flags);
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for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
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int i = irq >> 5;
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level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
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desc->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &pmac_pic, level ?
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handle_level_irq : handle_edge_irq);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &pmac_pic,
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level ? handle_level_irq : handle_edge_irq);
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static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
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struct mpic *mpic = desc->handler_data;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct mpic *mpic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = mpic_get_one_irq(mpic);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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desc->chip->eoi(irq);
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chip->irq_eoi(&desc->irq_data);
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static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
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of_node_put(slave);
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set_irq_data(cascade, mpic2);
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set_irq_chained_handler(cascade, pmac_u3_cascade);
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irq_set_handler_data(cascade, mpic2);
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irq_set_chained_handler(cascade, pmac_u3_cascade);
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of_node_put(slave);
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for (i = 0; i < max_real_irqs; ++i)
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if (test_bit(i, sleep_save_mask))
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pmac_unmask_irq(irq_get_irq_data(i));
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#endif /* CONFIG_PM && CONFIG_PPC32 */
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static struct sysdev_class pmacpic_sysclass = {
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static struct sys_device device_pmacpic = {
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.cls = &pmacpic_sysclass,
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static struct sysdev_driver driver_pmacpic = {
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#if defined(CONFIG_PM) && defined(CONFIG_PPC32)
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.suspend = &pmacpic_suspend,
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.resume = &pmacpic_resume,
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#endif /* CONFIG_PM && CONFIG_PPC32 */
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static int __init init_pmacpic_sysfs(void)
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static struct syscore_ops pmacpic_syscore_ops = {
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.suspend = pmacpic_suspend,
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.resume = pmacpic_resume,
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static int __init init_pmacpic_syscore(void)
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printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
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sysdev_class_register(&pmacpic_sysclass);
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sysdev_register(&device_pmacpic);
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sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
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register_syscore_ops(&pmacpic_syscore_ops);
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machine_subsys_initcall(powermac, init_pmacpic_sysfs);
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machine_subsys_initcall(powermac, init_pmacpic_syscore);
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#endif /* CONFIG_PM && CONFIG_PPC32 */