2
* linux/arch/arm/plat-omap/gpio.c
4
* Support functions for OMAP GPIO
6
* Copyright (C) 2003-2005 Nokia Corporation
7
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
9
* Copyright (C) 2009 Texas Instruments
10
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12
* This program is free software; you can redistribute it and/or modify
13
* it under the terms of the GNU General Public License version 2 as
14
* published by the Free Software Foundation.
17
#include <linux/init.h>
18
#include <linux/module.h>
19
#include <linux/interrupt.h>
20
#include <linux/sysdev.h>
21
#include <linux/err.h>
22
#include <linux/clk.h>
24
#include <linux/slab.h>
25
#include <linux/pm_runtime.h>
27
#include <mach/hardware.h>
29
#include <mach/irqs.h>
30
#include <mach/gpio.h>
31
#include <asm/mach/irq.h>
34
* OMAP1510 GPIO registers
36
#define OMAP1510_GPIO_DATA_INPUT 0x00
37
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38
#define OMAP1510_GPIO_DIR_CONTROL 0x08
39
#define OMAP1510_GPIO_INT_CONTROL 0x0c
40
#define OMAP1510_GPIO_INT_MASK 0x10
41
#define OMAP1510_GPIO_INT_STATUS 0x14
42
#define OMAP1510_GPIO_PIN_CONTROL 0x18
44
#define OMAP1510_IH_GPIO_BASE 64
47
* OMAP1610 specific GPIO registers
49
#define OMAP1610_GPIO_REVISION 0x0000
50
#define OMAP1610_GPIO_SYSCONFIG 0x0010
51
#define OMAP1610_GPIO_SYSSTATUS 0x0014
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#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53
#define OMAP1610_GPIO_IRQENABLE1 0x001c
54
#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55
#define OMAP1610_GPIO_DATAIN 0x002c
56
#define OMAP1610_GPIO_DATAOUT 0x0030
57
#define OMAP1610_GPIO_DIRECTION 0x0034
58
#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59
#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
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#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61
#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62
#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
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#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
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#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65
#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
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* OMAP7XX specific GPIO registers
70
#define OMAP7XX_GPIO_DATA_INPUT 0x00
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#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
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#define OMAP7XX_GPIO_DIR_CONTROL 0x08
73
#define OMAP7XX_GPIO_INT_CONTROL 0x0c
74
#define OMAP7XX_GPIO_INT_MASK 0x10
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#define OMAP7XX_GPIO_INT_STATUS 0x14
78
* omap2+ specific GPIO registers
80
#define OMAP24XX_GPIO_REVISION 0x0000
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#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
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#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83
#define OMAP24XX_GPIO_IRQENABLE2 0x002c
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#define OMAP24XX_GPIO_IRQENABLE1 0x001c
85
#define OMAP24XX_GPIO_WAKE_EN 0x0020
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#define OMAP24XX_GPIO_CTRL 0x0030
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#define OMAP24XX_GPIO_OE 0x0034
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#define OMAP24XX_GPIO_DATAIN 0x0038
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#define OMAP24XX_GPIO_DATAOUT 0x003c
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#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
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#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
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#define OMAP24XX_GPIO_RISINGDETECT 0x0048
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#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
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#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
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#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
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#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97
#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
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#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
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#define OMAP24XX_GPIO_SETWKUENA 0x0084
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#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
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#define OMAP24XX_GPIO_SETDATAOUT 0x0094
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#define OMAP4_GPIO_REVISION 0x0000
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#define OMAP4_GPIO_EOI 0x0020
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#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
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#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
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#define OMAP4_GPIO_IRQSTATUS0 0x002c
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#define OMAP4_GPIO_IRQSTATUS1 0x0030
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#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
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#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
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#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112
#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
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#define OMAP4_GPIO_IRQWAKEN0 0x0044
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#define OMAP4_GPIO_IRQWAKEN1 0x0048
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#define OMAP4_GPIO_IRQENABLE1 0x011c
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#define OMAP4_GPIO_WAKE_EN 0x0120
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#define OMAP4_GPIO_IRQSTATUS2 0x0128
118
#define OMAP4_GPIO_IRQENABLE2 0x012c
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#define OMAP4_GPIO_CTRL 0x0130
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#define OMAP4_GPIO_OE 0x0134
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#define OMAP4_GPIO_DATAIN 0x0138
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#define OMAP4_GPIO_DATAOUT 0x013c
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#define OMAP4_GPIO_LEVELDETECT0 0x0140
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#define OMAP4_GPIO_LEVELDETECT1 0x0144
125
#define OMAP4_GPIO_RISINGDETECT 0x0148
126
#define OMAP4_GPIO_FALLINGDETECT 0x014c
127
#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128
#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
129
#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130
#define OMAP4_GPIO_SETIRQENABLE1 0x0164
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#define OMAP4_GPIO_CLEARWKUENA 0x0180
132
#define OMAP4_GPIO_SETWKUENA 0x0184
133
#define OMAP4_GPIO_CLEARDATAOUT 0x0190
134
#define OMAP4_GPIO_SETDATAOUT 0x0194
140
u16 virtual_irq_start;
142
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
146
u32 non_wakeup_gpios;
147
u32 enabled_non_wakeup_gpios;
150
u32 saved_fallingdetect;
151
u32 saved_risingdetect;
155
struct gpio_chip chip;
158
u32 dbck_enable_mask;
164
#ifdef CONFIG_ARCH_OMAP3
165
struct omap3_gpio_regs {
178
static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
182
* TODO: Cleanup gpio_bank usage as it is having information
183
* related to all instances of the device
185
static struct gpio_bank *gpio_bank;
187
static int bank_width;
189
/* TODO: Analyze removing gpio_bank_count usage from driver code */
192
static inline struct gpio_bank *get_gpio_bank(int gpio)
194
if (cpu_is_omap15xx()) {
195
if (OMAP_GPIO_IS_MPUIO(gpio))
196
return &gpio_bank[0];
197
return &gpio_bank[1];
199
if (cpu_is_omap16xx()) {
200
if (OMAP_GPIO_IS_MPUIO(gpio))
201
return &gpio_bank[0];
202
return &gpio_bank[1 + (gpio >> 4)];
204
if (cpu_is_omap7xx()) {
205
if (OMAP_GPIO_IS_MPUIO(gpio))
206
return &gpio_bank[0];
207
return &gpio_bank[1 + (gpio >> 5)];
209
if (cpu_is_omap24xx())
210
return &gpio_bank[gpio >> 5];
211
if (cpu_is_omap34xx() || cpu_is_omap44xx())
212
return &gpio_bank[gpio >> 5];
217
static inline int get_gpio_index(int gpio)
219
if (cpu_is_omap7xx())
221
if (cpu_is_omap24xx())
223
if (cpu_is_omap34xx() || cpu_is_omap44xx())
228
static inline int gpio_valid(int gpio)
232
if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
233
if (gpio >= OMAP_MAX_GPIO_LINES + 16)
237
if (cpu_is_omap15xx() && gpio < 16)
239
if ((cpu_is_omap16xx()) && gpio < 64)
241
if (cpu_is_omap7xx() && gpio < 192)
243
if (cpu_is_omap2420() && gpio < 128)
245
if (cpu_is_omap2430() && gpio < 160)
247
if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
252
static int check_gpio(int gpio)
254
if (unlikely(gpio_valid(gpio) < 0)) {
255
printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
262
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
264
void __iomem *reg = bank->base;
267
switch (bank->method) {
268
#ifdef CONFIG_ARCH_OMAP1
270
reg += OMAP_MPUIO_IO_CNTL / bank->stride;
273
#ifdef CONFIG_ARCH_OMAP15XX
274
case METHOD_GPIO_1510:
275
reg += OMAP1510_GPIO_DIR_CONTROL;
278
#ifdef CONFIG_ARCH_OMAP16XX
279
case METHOD_GPIO_1610:
280
reg += OMAP1610_GPIO_DIRECTION;
283
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
284
case METHOD_GPIO_7XX:
285
reg += OMAP7XX_GPIO_DIR_CONTROL;
288
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
289
case METHOD_GPIO_24XX:
290
reg += OMAP24XX_GPIO_OE;
293
#if defined(CONFIG_ARCH_OMAP4)
294
case METHOD_GPIO_44XX:
295
reg += OMAP4_GPIO_OE;
302
l = __raw_readl(reg);
307
__raw_writel(l, reg);
310
static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
312
void __iomem *reg = bank->base;
315
switch (bank->method) {
316
#ifdef CONFIG_ARCH_OMAP1
318
reg += OMAP_MPUIO_OUTPUT / bank->stride;
319
l = __raw_readl(reg);
326
#ifdef CONFIG_ARCH_OMAP15XX
327
case METHOD_GPIO_1510:
328
reg += OMAP1510_GPIO_DATA_OUTPUT;
329
l = __raw_readl(reg);
336
#ifdef CONFIG_ARCH_OMAP16XX
337
case METHOD_GPIO_1610:
339
reg += OMAP1610_GPIO_SET_DATAOUT;
341
reg += OMAP1610_GPIO_CLEAR_DATAOUT;
345
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
346
case METHOD_GPIO_7XX:
347
reg += OMAP7XX_GPIO_DATA_OUTPUT;
348
l = __raw_readl(reg);
355
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
356
case METHOD_GPIO_24XX:
358
reg += OMAP24XX_GPIO_SETDATAOUT;
360
reg += OMAP24XX_GPIO_CLEARDATAOUT;
364
#ifdef CONFIG_ARCH_OMAP4
365
case METHOD_GPIO_44XX:
367
reg += OMAP4_GPIO_SETDATAOUT;
369
reg += OMAP4_GPIO_CLEARDATAOUT;
377
__raw_writel(l, reg);
380
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
384
if (check_gpio(gpio) < 0)
387
switch (bank->method) {
388
#ifdef CONFIG_ARCH_OMAP1
390
reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
393
#ifdef CONFIG_ARCH_OMAP15XX
394
case METHOD_GPIO_1510:
395
reg += OMAP1510_GPIO_DATA_INPUT;
398
#ifdef CONFIG_ARCH_OMAP16XX
399
case METHOD_GPIO_1610:
400
reg += OMAP1610_GPIO_DATAIN;
403
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
404
case METHOD_GPIO_7XX:
405
reg += OMAP7XX_GPIO_DATA_INPUT;
408
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
409
case METHOD_GPIO_24XX:
410
reg += OMAP24XX_GPIO_DATAIN;
413
#ifdef CONFIG_ARCH_OMAP4
414
case METHOD_GPIO_44XX:
415
reg += OMAP4_GPIO_DATAIN;
421
return (__raw_readl(reg)
422
& (1 << get_gpio_index(gpio))) != 0;
425
static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
429
if (check_gpio(gpio) < 0)
433
switch (bank->method) {
434
#ifdef CONFIG_ARCH_OMAP1
436
reg += OMAP_MPUIO_OUTPUT / bank->stride;
439
#ifdef CONFIG_ARCH_OMAP15XX
440
case METHOD_GPIO_1510:
441
reg += OMAP1510_GPIO_DATA_OUTPUT;
444
#ifdef CONFIG_ARCH_OMAP16XX
445
case METHOD_GPIO_1610:
446
reg += OMAP1610_GPIO_DATAOUT;
449
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
450
case METHOD_GPIO_7XX:
451
reg += OMAP7XX_GPIO_DATA_OUTPUT;
454
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
455
case METHOD_GPIO_24XX:
456
reg += OMAP24XX_GPIO_DATAOUT;
459
#ifdef CONFIG_ARCH_OMAP4
460
case METHOD_GPIO_44XX:
461
reg += OMAP4_GPIO_DATAOUT;
468
return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
471
#define MOD_REG_BIT(reg, bit_mask, set) \
473
int l = __raw_readl(base + reg); \
474
if (set) l |= bit_mask; \
475
else l &= ~bit_mask; \
476
__raw_writel(l, base + reg); \
480
* _set_gpio_debounce - low level gpio debounce time
481
* @bank: the gpio bank we're acting upon
482
* @gpio: the gpio number on this @gpio
483
* @debounce: debounce time to use
485
* OMAP's debounce time is in 31us steps so we need
486
* to convert and round up to the closest unit.
488
static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
491
void __iomem *reg = bank->base;
495
if (!bank->dbck_flag)
500
else if (debounce > 7936)
503
debounce = (debounce / 0x1f) - 1;
505
l = 1 << get_gpio_index(gpio);
507
if (bank->method == METHOD_GPIO_44XX)
508
reg += OMAP4_GPIO_DEBOUNCINGTIME;
510
reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
512
__raw_writel(debounce, reg);
515
if (bank->method == METHOD_GPIO_44XX)
516
reg += OMAP4_GPIO_DEBOUNCENABLE;
518
reg += OMAP24XX_GPIO_DEBOUNCE_EN;
520
val = __raw_readl(reg);
524
clk_enable(bank->dbck);
527
clk_disable(bank->dbck);
529
bank->dbck_enable_mask = val;
531
__raw_writel(val, reg);
534
#ifdef CONFIG_ARCH_OMAP2PLUS
535
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
538
void __iomem *base = bank->base;
539
u32 gpio_bit = 1 << gpio;
542
if (cpu_is_omap44xx()) {
543
MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544
trigger & IRQ_TYPE_LEVEL_LOW);
545
MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546
trigger & IRQ_TYPE_LEVEL_HIGH);
547
MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548
trigger & IRQ_TYPE_EDGE_RISING);
549
MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550
trigger & IRQ_TYPE_EDGE_FALLING);
552
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553
trigger & IRQ_TYPE_LEVEL_LOW);
554
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555
trigger & IRQ_TYPE_LEVEL_HIGH);
556
MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557
trigger & IRQ_TYPE_EDGE_RISING);
558
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559
trigger & IRQ_TYPE_EDGE_FALLING);
561
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
562
if (cpu_is_omap44xx()) {
564
__raw_writel(1 << gpio, bank->base+
565
OMAP4_GPIO_IRQWAKEN0);
567
val = __raw_readl(bank->base +
568
OMAP4_GPIO_IRQWAKEN0);
569
__raw_writel(val & (~(1 << gpio)), bank->base +
570
OMAP4_GPIO_IRQWAKEN0);
574
* GPIO wakeup request can only be generated on edge
577
if (trigger & IRQ_TYPE_EDGE_BOTH)
578
__raw_writel(1 << gpio, bank->base
579
+ OMAP24XX_GPIO_SETWKUENA);
581
__raw_writel(1 << gpio, bank->base
582
+ OMAP24XX_GPIO_CLEARWKUENA);
585
/* This part needs to be executed always for OMAP34xx */
586
if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
588
* Log the edge gpio and manually trigger the IRQ
589
* after resume if the input level changes
590
* to avoid irq lost during PER RET/OFF mode
591
* Applies for omap2 non-wakeup gpio and all omap3 gpios
593
if (trigger & IRQ_TYPE_EDGE_BOTH)
594
bank->enabled_non_wakeup_gpios |= gpio_bit;
596
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
599
if (cpu_is_omap44xx()) {
601
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
605
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
611
#ifdef CONFIG_ARCH_OMAP1
613
* This only applies to chips that can't do both rising and falling edge
614
* detection at once. For all other chips, this function is a noop.
616
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
618
void __iomem *reg = bank->base;
621
switch (bank->method) {
623
reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
625
#ifdef CONFIG_ARCH_OMAP15XX
626
case METHOD_GPIO_1510:
627
reg += OMAP1510_GPIO_INT_CONTROL;
630
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631
case METHOD_GPIO_7XX:
632
reg += OMAP7XX_GPIO_INT_CONTROL;
639
l = __raw_readl(reg);
645
__raw_writel(l, reg);
649
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
651
void __iomem *reg = bank->base;
654
switch (bank->method) {
655
#ifdef CONFIG_ARCH_OMAP1
657
reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
658
l = __raw_readl(reg);
659
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
660
bank->toggle_mask |= 1 << gpio;
661
if (trigger & IRQ_TYPE_EDGE_RISING)
663
else if (trigger & IRQ_TYPE_EDGE_FALLING)
669
#ifdef CONFIG_ARCH_OMAP15XX
670
case METHOD_GPIO_1510:
671
reg += OMAP1510_GPIO_INT_CONTROL;
672
l = __raw_readl(reg);
673
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
674
bank->toggle_mask |= 1 << gpio;
675
if (trigger & IRQ_TYPE_EDGE_RISING)
677
else if (trigger & IRQ_TYPE_EDGE_FALLING)
683
#ifdef CONFIG_ARCH_OMAP16XX
684
case METHOD_GPIO_1610:
686
reg += OMAP1610_GPIO_EDGE_CTRL2;
688
reg += OMAP1610_GPIO_EDGE_CTRL1;
690
l = __raw_readl(reg);
691
l &= ~(3 << (gpio << 1));
692
if (trigger & IRQ_TYPE_EDGE_RISING)
693
l |= 2 << (gpio << 1);
694
if (trigger & IRQ_TYPE_EDGE_FALLING)
695
l |= 1 << (gpio << 1);
697
/* Enable wake-up during idle for dynamic tick */
698
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
700
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
703
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
704
case METHOD_GPIO_7XX:
705
reg += OMAP7XX_GPIO_INT_CONTROL;
706
l = __raw_readl(reg);
707
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
708
bank->toggle_mask |= 1 << gpio;
709
if (trigger & IRQ_TYPE_EDGE_RISING)
711
else if (trigger & IRQ_TYPE_EDGE_FALLING)
717
#ifdef CONFIG_ARCH_OMAP2PLUS
718
case METHOD_GPIO_24XX:
719
case METHOD_GPIO_44XX:
720
set_24xx_gpio_triggering(bank, gpio, trigger);
726
__raw_writel(l, reg);
732
static int gpio_irq_type(struct irq_data *d, unsigned type)
734
struct gpio_bank *bank;
739
if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
740
gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
742
gpio = d->irq - IH_GPIO_BASE;
744
if (check_gpio(gpio) < 0)
747
if (type & ~IRQ_TYPE_SENSE_MASK)
750
/* OMAP1 allows only only edge triggering */
751
if (!cpu_class_is_omap2()
752
&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
755
bank = irq_data_get_irq_chip_data(d);
756
spin_lock_irqsave(&bank->lock, flags);
757
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
759
struct irq_desc *desc = irq_to_desc(d->irq);
761
desc->status &= ~IRQ_TYPE_SENSE_MASK;
762
desc->status |= type;
764
spin_unlock_irqrestore(&bank->lock, flags);
766
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
767
__set_irq_handler_unlocked(d->irq, handle_level_irq);
768
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
769
__set_irq_handler_unlocked(d->irq, handle_edge_irq);
774
static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
776
void __iomem *reg = bank->base;
778
switch (bank->method) {
779
#ifdef CONFIG_ARCH_OMAP1
781
/* MPUIO irqstatus is reset by reading the status register,
782
* so do nothing here */
785
#ifdef CONFIG_ARCH_OMAP15XX
786
case METHOD_GPIO_1510:
787
reg += OMAP1510_GPIO_INT_STATUS;
790
#ifdef CONFIG_ARCH_OMAP16XX
791
case METHOD_GPIO_1610:
792
reg += OMAP1610_GPIO_IRQSTATUS1;
795
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
796
case METHOD_GPIO_7XX:
797
reg += OMAP7XX_GPIO_INT_STATUS;
800
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
801
case METHOD_GPIO_24XX:
802
reg += OMAP24XX_GPIO_IRQSTATUS1;
805
#if defined(CONFIG_ARCH_OMAP4)
806
case METHOD_GPIO_44XX:
807
reg += OMAP4_GPIO_IRQSTATUS0;
814
__raw_writel(gpio_mask, reg);
816
/* Workaround for clearing DSP GPIO interrupts to allow retention */
817
if (cpu_is_omap24xx() || cpu_is_omap34xx())
818
reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
819
else if (cpu_is_omap44xx())
820
reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
822
if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
823
__raw_writel(gpio_mask, reg);
825
/* Flush posted write for the irq status to avoid spurious interrupts */
830
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
832
_clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
835
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
837
void __iomem *reg = bank->base;
842
switch (bank->method) {
843
#ifdef CONFIG_ARCH_OMAP1
845
reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
850
#ifdef CONFIG_ARCH_OMAP15XX
851
case METHOD_GPIO_1510:
852
reg += OMAP1510_GPIO_INT_MASK;
857
#ifdef CONFIG_ARCH_OMAP16XX
858
case METHOD_GPIO_1610:
859
reg += OMAP1610_GPIO_IRQENABLE1;
863
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
864
case METHOD_GPIO_7XX:
865
reg += OMAP7XX_GPIO_INT_MASK;
870
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
871
case METHOD_GPIO_24XX:
872
reg += OMAP24XX_GPIO_IRQENABLE1;
876
#if defined(CONFIG_ARCH_OMAP4)
877
case METHOD_GPIO_44XX:
878
reg += OMAP4_GPIO_IRQSTATUSSET0;
887
l = __raw_readl(reg);
894
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
896
void __iomem *reg = bank->base;
899
switch (bank->method) {
900
#ifdef CONFIG_ARCH_OMAP1
902
reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
903
l = __raw_readl(reg);
910
#ifdef CONFIG_ARCH_OMAP15XX
911
case METHOD_GPIO_1510:
912
reg += OMAP1510_GPIO_INT_MASK;
913
l = __raw_readl(reg);
920
#ifdef CONFIG_ARCH_OMAP16XX
921
case METHOD_GPIO_1610:
923
reg += OMAP1610_GPIO_SET_IRQENABLE1;
925
reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
929
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
930
case METHOD_GPIO_7XX:
931
reg += OMAP7XX_GPIO_INT_MASK;
932
l = __raw_readl(reg);
939
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
940
case METHOD_GPIO_24XX:
942
reg += OMAP24XX_GPIO_SETIRQENABLE1;
944
reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
948
#ifdef CONFIG_ARCH_OMAP4
949
case METHOD_GPIO_44XX:
951
reg += OMAP4_GPIO_IRQSTATUSSET0;
953
reg += OMAP4_GPIO_IRQSTATUSCLR0;
961
__raw_writel(l, reg);
964
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
966
_enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
970
* Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
971
* 1510 does not seem to have a wake-up register. If JTAG is connected
972
* to the target, system will wake up always on GPIO events. While
973
* system is running all registered GPIO interrupts need to have wake-up
974
* enabled. When system is suspended, only selected GPIO interrupts need
975
* to have wake-up enabled.
977
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
979
unsigned long uninitialized_var(flags);
981
switch (bank->method) {
982
#ifdef CONFIG_ARCH_OMAP16XX
984
case METHOD_GPIO_1610:
985
spin_lock_irqsave(&bank->lock, flags);
987
bank->suspend_wakeup |= (1 << gpio);
989
bank->suspend_wakeup &= ~(1 << gpio);
990
spin_unlock_irqrestore(&bank->lock, flags);
993
#ifdef CONFIG_ARCH_OMAP2PLUS
994
case METHOD_GPIO_24XX:
995
case METHOD_GPIO_44XX:
996
if (bank->non_wakeup_gpios & (1 << gpio)) {
997
printk(KERN_ERR "Unable to modify wakeup on "
998
"non-wakeup GPIO%d\n",
999
(bank - gpio_bank) * 32 + gpio);
1002
spin_lock_irqsave(&bank->lock, flags);
1004
bank->suspend_wakeup |= (1 << gpio);
1006
bank->suspend_wakeup &= ~(1 << gpio);
1007
spin_unlock_irqrestore(&bank->lock, flags);
1011
printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1017
static void _reset_gpio(struct gpio_bank *bank, int gpio)
1019
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
1020
_set_gpio_irqenable(bank, gpio, 0);
1021
_clear_gpio_irqstatus(bank, gpio);
1022
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1025
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1026
static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
1028
unsigned int gpio = d->irq - IH_GPIO_BASE;
1029
struct gpio_bank *bank;
1032
if (check_gpio(gpio) < 0)
1034
bank = irq_data_get_irq_chip_data(d);
1035
retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1040
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1042
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1043
unsigned long flags;
1045
spin_lock_irqsave(&bank->lock, flags);
1047
/* Set trigger to none. You need to enable the desired trigger with
1048
* request_irq() or set_irq_type().
1050
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1052
#ifdef CONFIG_ARCH_OMAP15XX
1053
if (bank->method == METHOD_GPIO_1510) {
1056
/* Claim the pin for MPU */
1057
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1058
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
1061
if (!cpu_class_is_omap1()) {
1062
if (!bank->mod_usage) {
1063
void __iomem *reg = bank->base;
1066
if (cpu_is_omap24xx() || cpu_is_omap34xx())
1067
reg += OMAP24XX_GPIO_CTRL;
1068
else if (cpu_is_omap44xx())
1069
reg += OMAP4_GPIO_CTRL;
1070
ctrl = __raw_readl(reg);
1071
/* Module is enabled, clocks are not gated */
1073
__raw_writel(ctrl, reg);
1075
bank->mod_usage |= 1 << offset;
1077
spin_unlock_irqrestore(&bank->lock, flags);
1082
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1084
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1085
unsigned long flags;
1087
spin_lock_irqsave(&bank->lock, flags);
1088
#ifdef CONFIG_ARCH_OMAP16XX
1089
if (bank->method == METHOD_GPIO_1610) {
1090
/* Disable wake-up during idle for dynamic tick */
1091
void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1092
__raw_writel(1 << offset, reg);
1095
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1096
if (bank->method == METHOD_GPIO_24XX) {
1097
/* Disable wake-up during idle for dynamic tick */
1098
void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1099
__raw_writel(1 << offset, reg);
1102
#ifdef CONFIG_ARCH_OMAP4
1103
if (bank->method == METHOD_GPIO_44XX) {
1104
/* Disable wake-up during idle for dynamic tick */
1105
void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1106
__raw_writel(1 << offset, reg);
1109
if (!cpu_class_is_omap1()) {
1110
bank->mod_usage &= ~(1 << offset);
1111
if (!bank->mod_usage) {
1112
void __iomem *reg = bank->base;
1115
if (cpu_is_omap24xx() || cpu_is_omap34xx())
1116
reg += OMAP24XX_GPIO_CTRL;
1117
else if (cpu_is_omap44xx())
1118
reg += OMAP4_GPIO_CTRL;
1119
ctrl = __raw_readl(reg);
1120
/* Module is disabled, clocks are gated */
1122
__raw_writel(ctrl, reg);
1125
_reset_gpio(bank, bank->chip.base + offset);
1126
spin_unlock_irqrestore(&bank->lock, flags);
1130
* We need to unmask the GPIO bank interrupt as soon as possible to
1131
* avoid missing GPIO interrupts for other lines in the bank.
1132
* Then we need to mask-read-clear-unmask the triggered GPIO lines
1133
* in the bank to avoid missing nested interrupts for a GPIO line.
1134
* If we wait to unmask individual GPIO lines in the bank after the
1135
* line's interrupt handler has been run, we may miss some nested
1138
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1140
void __iomem *isr_reg = NULL;
1142
unsigned int gpio_irq, gpio_index;
1143
struct gpio_bank *bank;
1147
desc->irq_data.chip->irq_ack(&desc->irq_data);
1149
bank = get_irq_data(irq);
1150
#ifdef CONFIG_ARCH_OMAP1
1151
if (bank->method == METHOD_MPUIO)
1152
isr_reg = bank->base +
1153
OMAP_MPUIO_GPIO_INT / bank->stride;
1155
#ifdef CONFIG_ARCH_OMAP15XX
1156
if (bank->method == METHOD_GPIO_1510)
1157
isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1159
#if defined(CONFIG_ARCH_OMAP16XX)
1160
if (bank->method == METHOD_GPIO_1610)
1161
isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1163
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1164
if (bank->method == METHOD_GPIO_7XX)
1165
isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1167
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1168
if (bank->method == METHOD_GPIO_24XX)
1169
isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1171
#if defined(CONFIG_ARCH_OMAP4)
1172
if (bank->method == METHOD_GPIO_44XX)
1173
isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1176
if (WARN_ON(!isr_reg))
1180
u32 isr_saved, level_mask = 0;
1183
enabled = _get_gpio_irqbank_mask(bank);
1184
isr_saved = isr = __raw_readl(isr_reg) & enabled;
1186
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1189
if (cpu_class_is_omap2()) {
1190
level_mask = bank->level_mask & enabled;
1193
/* clear edge sensitive interrupts before handler(s) are
1194
called so that we don't miss any interrupt occurred while
1196
_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1197
_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1198
_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1200
/* if there is only edge sensitive GPIO pin interrupts
1201
configured, we could unmask GPIO bank interrupt immediately */
1202
if (!level_mask && !unmasked) {
1204
desc->irq_data.chip->irq_unmask(&desc->irq_data);
1212
gpio_irq = bank->virtual_irq_start;
1213
for (; isr != 0; isr >>= 1, gpio_irq++) {
1214
gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1219
#ifdef CONFIG_ARCH_OMAP1
1221
* Some chips can't respond to both rising and falling
1222
* at the same time. If this irq was requested with
1223
* both flags, we need to flip the ICR data for the IRQ
1224
* to respond to the IRQ for the opposite direction.
1225
* This will be indicated in the bank toggle_mask.
1227
if (bank->toggle_mask & (1 << gpio_index))
1228
_toggle_gpio_edge_triggering(bank, gpio_index);
1231
generic_handle_irq(gpio_irq);
1234
/* if bank has any level sensitive GPIO pin interrupt
1235
configured, we must unmask the bank interrupt only after
1236
handler(s) are executed in order to avoid spurious bank
1240
desc->irq_data.chip->irq_unmask(&desc->irq_data);
1243
static void gpio_irq_shutdown(struct irq_data *d)
1245
unsigned int gpio = d->irq - IH_GPIO_BASE;
1246
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1248
_reset_gpio(bank, gpio);
1251
static void gpio_ack_irq(struct irq_data *d)
1253
unsigned int gpio = d->irq - IH_GPIO_BASE;
1254
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1256
_clear_gpio_irqstatus(bank, gpio);
1259
static void gpio_mask_irq(struct irq_data *d)
1261
unsigned int gpio = d->irq - IH_GPIO_BASE;
1262
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1264
_set_gpio_irqenable(bank, gpio, 0);
1265
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1268
static void gpio_unmask_irq(struct irq_data *d)
1270
unsigned int gpio = d->irq - IH_GPIO_BASE;
1271
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1272
unsigned int irq_mask = 1 << get_gpio_index(gpio);
1273
struct irq_desc *desc = irq_to_desc(d->irq);
1274
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1277
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1279
/* For level-triggered GPIOs, the clearing must be done after
1280
* the HW source is cleared, thus after the handler has run */
1281
if (bank->level_mask & irq_mask) {
1282
_set_gpio_irqenable(bank, gpio, 0);
1283
_clear_gpio_irqstatus(bank, gpio);
1286
_set_gpio_irqenable(bank, gpio, 1);
1289
static struct irq_chip gpio_irq_chip = {
1291
.irq_shutdown = gpio_irq_shutdown,
1292
.irq_ack = gpio_ack_irq,
1293
.irq_mask = gpio_mask_irq,
1294
.irq_unmask = gpio_unmask_irq,
1295
.irq_set_type = gpio_irq_type,
1296
.irq_set_wake = gpio_wake_enable,
1299
/*---------------------------------------------------------------------*/
1301
#ifdef CONFIG_ARCH_OMAP1
1303
/* MPUIO uses the always-on 32k clock */
1305
static void mpuio_ack_irq(struct irq_data *d)
1307
/* The ISR is reset automatically, so do nothing here. */
1310
static void mpuio_mask_irq(struct irq_data *d)
1312
unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1313
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1315
_set_gpio_irqenable(bank, gpio, 0);
1318
static void mpuio_unmask_irq(struct irq_data *d)
1320
unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1321
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1323
_set_gpio_irqenable(bank, gpio, 1);
1326
static struct irq_chip mpuio_irq_chip = {
1328
.irq_ack = mpuio_ack_irq,
1329
.irq_mask = mpuio_mask_irq,
1330
.irq_unmask = mpuio_unmask_irq,
1331
.irq_set_type = gpio_irq_type,
1332
#ifdef CONFIG_ARCH_OMAP16XX
1333
/* REVISIT: assuming only 16xx supports MPUIO wake events */
1334
.irq_set_wake = gpio_wake_enable,
1339
#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1342
#ifdef CONFIG_ARCH_OMAP16XX
1344
#include <linux/platform_device.h>
1346
static int omap_mpuio_suspend_noirq(struct device *dev)
1348
struct platform_device *pdev = to_platform_device(dev);
1349
struct gpio_bank *bank = platform_get_drvdata(pdev);
1350
void __iomem *mask_reg = bank->base +
1351
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1352
unsigned long flags;
1354
spin_lock_irqsave(&bank->lock, flags);
1355
bank->saved_wakeup = __raw_readl(mask_reg);
1356
__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1357
spin_unlock_irqrestore(&bank->lock, flags);
1362
static int omap_mpuio_resume_noirq(struct device *dev)
1364
struct platform_device *pdev = to_platform_device(dev);
1365
struct gpio_bank *bank = platform_get_drvdata(pdev);
1366
void __iomem *mask_reg = bank->base +
1367
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1368
unsigned long flags;
1370
spin_lock_irqsave(&bank->lock, flags);
1371
__raw_writel(bank->saved_wakeup, mask_reg);
1372
spin_unlock_irqrestore(&bank->lock, flags);
1377
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1378
.suspend_noirq = omap_mpuio_suspend_noirq,
1379
.resume_noirq = omap_mpuio_resume_noirq,
1382
/* use platform_driver for this, now that there's no longer any
1383
* point to sys_device (other than not disturbing old code).
1385
static struct platform_driver omap_mpuio_driver = {
1388
.pm = &omap_mpuio_dev_pm_ops,
1392
static struct platform_device omap_mpuio_device = {
1396
.driver = &omap_mpuio_driver.driver,
1398
/* could list the /proc/iomem resources */
1401
static inline void mpuio_init(void)
1403
struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1404
platform_set_drvdata(&omap_mpuio_device, bank);
1406
if (platform_driver_register(&omap_mpuio_driver) == 0)
1407
(void) platform_device_register(&omap_mpuio_device);
1411
static inline void mpuio_init(void) {}
1416
extern struct irq_chip mpuio_irq_chip;
1418
#define bank_is_mpuio(bank) 0
1419
static inline void mpuio_init(void) {}
1423
/*---------------------------------------------------------------------*/
1425
/* REVISIT these are stupid implementations! replace by ones that
1426
* don't switch on METHOD_* and which mostly avoid spinlocks
1429
static int gpio_input(struct gpio_chip *chip, unsigned offset)
1431
struct gpio_bank *bank;
1432
unsigned long flags;
1434
bank = container_of(chip, struct gpio_bank, chip);
1435
spin_lock_irqsave(&bank->lock, flags);
1436
_set_gpio_direction(bank, offset, 1);
1437
spin_unlock_irqrestore(&bank->lock, flags);
1441
static int gpio_is_input(struct gpio_bank *bank, int mask)
1443
void __iomem *reg = bank->base;
1445
switch (bank->method) {
1447
reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1449
case METHOD_GPIO_1510:
1450
reg += OMAP1510_GPIO_DIR_CONTROL;
1452
case METHOD_GPIO_1610:
1453
reg += OMAP1610_GPIO_DIRECTION;
1455
case METHOD_GPIO_7XX:
1456
reg += OMAP7XX_GPIO_DIR_CONTROL;
1458
case METHOD_GPIO_24XX:
1459
reg += OMAP24XX_GPIO_OE;
1461
case METHOD_GPIO_44XX:
1462
reg += OMAP4_GPIO_OE;
1465
WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1468
return __raw_readl(reg) & mask;
1471
static int gpio_get(struct gpio_chip *chip, unsigned offset)
1473
struct gpio_bank *bank;
1478
gpio = chip->base + offset;
1479
bank = get_gpio_bank(gpio);
1481
mask = 1 << get_gpio_index(gpio);
1483
if (gpio_is_input(bank, mask))
1484
return _get_gpio_datain(bank, gpio);
1486
return _get_gpio_dataout(bank, gpio);
1489
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1491
struct gpio_bank *bank;
1492
unsigned long flags;
1494
bank = container_of(chip, struct gpio_bank, chip);
1495
spin_lock_irqsave(&bank->lock, flags);
1496
_set_gpio_dataout(bank, offset, value);
1497
_set_gpio_direction(bank, offset, 0);
1498
spin_unlock_irqrestore(&bank->lock, flags);
1502
static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1505
struct gpio_bank *bank;
1506
unsigned long flags;
1508
bank = container_of(chip, struct gpio_bank, chip);
1511
bank->dbck = clk_get(bank->dev, "dbclk");
1512
if (IS_ERR(bank->dbck))
1513
dev_err(bank->dev, "Could not get gpio dbck\n");
1516
spin_lock_irqsave(&bank->lock, flags);
1517
_set_gpio_debounce(bank, offset, debounce);
1518
spin_unlock_irqrestore(&bank->lock, flags);
1523
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1525
struct gpio_bank *bank;
1526
unsigned long flags;
1528
bank = container_of(chip, struct gpio_bank, chip);
1529
spin_lock_irqsave(&bank->lock, flags);
1530
_set_gpio_dataout(bank, offset, value);
1531
spin_unlock_irqrestore(&bank->lock, flags);
1534
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1536
struct gpio_bank *bank;
1538
bank = container_of(chip, struct gpio_bank, chip);
1539
return bank->virtual_irq_start + offset;
1542
/*---------------------------------------------------------------------*/
1544
static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1548
if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1549
rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1550
else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1551
rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1552
else if (cpu_is_omap44xx())
1553
rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1557
printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1558
(rev >> 4) & 0x0f, rev & 0x0f);
1561
/* This lock class tells lockdep that GPIO irqs are in a different
1562
* category than their parents, so it won't report false recursion.
1564
static struct lock_class_key gpio_lock_class;
1566
static inline int init_gpio_info(struct platform_device *pdev)
1568
/* TODO: Analyze removing gpio_bank_count usage from driver code */
1569
gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1572
dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1578
/* TODO: Cleanup cpu_is_* checks */
1579
static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1581
if (cpu_class_is_omap2()) {
1582
if (cpu_is_omap44xx()) {
1583
__raw_writel(0xffffffff, bank->base +
1584
OMAP4_GPIO_IRQSTATUSCLR0);
1585
__raw_writel(0x00000000, bank->base +
1586
OMAP4_GPIO_DEBOUNCENABLE);
1587
/* Initialize interface clk ungated, module enabled */
1588
__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1589
} else if (cpu_is_omap34xx()) {
1590
__raw_writel(0x00000000, bank->base +
1591
OMAP24XX_GPIO_IRQENABLE1);
1592
__raw_writel(0xffffffff, bank->base +
1593
OMAP24XX_GPIO_IRQSTATUS1);
1594
__raw_writel(0x00000000, bank->base +
1595
OMAP24XX_GPIO_DEBOUNCE_EN);
1597
/* Initialize interface clk ungated, module enabled */
1598
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1599
} else if (cpu_is_omap24xx()) {
1600
static const u32 non_wakeup_gpios[] = {
1601
0xe203ffc0, 0x08700040
1603
if (id < ARRAY_SIZE(non_wakeup_gpios))
1604
bank->non_wakeup_gpios = non_wakeup_gpios[id];
1606
} else if (cpu_class_is_omap1()) {
1607
if (bank_is_mpuio(bank))
1608
__raw_writew(0xffff, bank->base +
1609
OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1610
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1611
__raw_writew(0xffff, bank->base
1612
+ OMAP1510_GPIO_INT_MASK);
1613
__raw_writew(0x0000, bank->base
1614
+ OMAP1510_GPIO_INT_STATUS);
1616
if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1617
__raw_writew(0x0000, bank->base
1618
+ OMAP1610_GPIO_IRQENABLE1);
1619
__raw_writew(0xffff, bank->base
1620
+ OMAP1610_GPIO_IRQSTATUS1);
1621
__raw_writew(0x0014, bank->base
1622
+ OMAP1610_GPIO_SYSCONFIG);
1625
* Enable system clock for GPIO module.
1626
* The CAM_CLK_CTRL *is* really the right place.
1628
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1631
if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1632
__raw_writel(0xffffffff, bank->base
1633
+ OMAP7XX_GPIO_INT_MASK);
1634
__raw_writel(0x00000000, bank->base
1635
+ OMAP7XX_GPIO_INT_STATUS);
1640
static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1645
bank->mod_usage = 0;
1647
* REVISIT eventually switch from OMAP-specific gpio structs
1648
* over to the generic ones
1650
bank->chip.request = omap_gpio_request;
1651
bank->chip.free = omap_gpio_free;
1652
bank->chip.direction_input = gpio_input;
1653
bank->chip.get = gpio_get;
1654
bank->chip.direction_output = gpio_output;
1655
bank->chip.set_debounce = gpio_debounce;
1656
bank->chip.set = gpio_set;
1657
bank->chip.to_irq = gpio_2irq;
1658
if (bank_is_mpuio(bank)) {
1659
bank->chip.label = "mpuio";
1660
#ifdef CONFIG_ARCH_OMAP16XX
1661
bank->chip.dev = &omap_mpuio_device.dev;
1663
bank->chip.base = OMAP_MPUIO(0);
1665
bank->chip.label = "gpio";
1666
bank->chip.base = gpio;
1669
bank->chip.ngpio = bank_width;
1671
gpiochip_add(&bank->chip);
1673
for (j = bank->virtual_irq_start;
1674
j < bank->virtual_irq_start + bank_width; j++) {
1675
struct irq_desc *d = irq_to_desc(j);
1677
lockdep_set_class(&d->lock, &gpio_lock_class);
1678
set_irq_chip_data(j, bank);
1679
if (bank_is_mpuio(bank))
1680
set_irq_chip(j, &mpuio_irq_chip);
1682
set_irq_chip(j, &gpio_irq_chip);
1683
set_irq_handler(j, handle_simple_irq);
1684
set_irq_flags(j, IRQF_VALID);
1686
set_irq_chained_handler(bank->irq, gpio_irq_handler);
1687
set_irq_data(bank->irq, bank);
1690
static int __devinit omap_gpio_probe(struct platform_device *pdev)
1692
static int gpio_init_done;
1693
struct omap_gpio_platform_data *pdata;
1694
struct resource *res;
1696
struct gpio_bank *bank;
1698
if (!pdev->dev.platform_data)
1701
pdata = pdev->dev.platform_data;
1703
if (!gpio_init_done) {
1706
ret = init_gpio_info(pdev);
1712
bank = &gpio_bank[id];
1714
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1715
if (unlikely(!res)) {
1716
dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1720
bank->irq = res->start;
1721
bank->virtual_irq_start = pdata->virtual_irq_start;
1722
bank->method = pdata->bank_type;
1723
bank->dev = &pdev->dev;
1724
bank->dbck_flag = pdata->dbck_flag;
1725
bank->stride = pdata->bank_stride;
1726
bank_width = pdata->bank_width;
1728
spin_lock_init(&bank->lock);
1730
/* Static mapping, never released */
1731
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1732
if (unlikely(!res)) {
1733
dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1737
bank->base = ioremap(res->start, resource_size(res));
1739
dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1743
pm_runtime_enable(bank->dev);
1744
pm_runtime_get_sync(bank->dev);
1746
omap_gpio_mod_init(bank, id);
1747
omap_gpio_chip_init(bank);
1748
omap_gpio_show_rev(bank);
1750
if (!gpio_init_done)
1756
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1757
static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1761
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1764
for (i = 0; i < gpio_bank_count; i++) {
1765
struct gpio_bank *bank = &gpio_bank[i];
1766
void __iomem *wake_status;
1767
void __iomem *wake_clear;
1768
void __iomem *wake_set;
1769
unsigned long flags;
1771
switch (bank->method) {
1772
#ifdef CONFIG_ARCH_OMAP16XX
1773
case METHOD_GPIO_1610:
1774
wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1775
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1776
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1779
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1780
case METHOD_GPIO_24XX:
1781
wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1782
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1783
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1786
#ifdef CONFIG_ARCH_OMAP4
1787
case METHOD_GPIO_44XX:
1788
wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1789
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1790
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1797
spin_lock_irqsave(&bank->lock, flags);
1798
bank->saved_wakeup = __raw_readl(wake_status);
1799
__raw_writel(0xffffffff, wake_clear);
1800
__raw_writel(bank->suspend_wakeup, wake_set);
1801
spin_unlock_irqrestore(&bank->lock, flags);
1807
static int omap_gpio_resume(struct sys_device *dev)
1811
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1814
for (i = 0; i < gpio_bank_count; i++) {
1815
struct gpio_bank *bank = &gpio_bank[i];
1816
void __iomem *wake_clear;
1817
void __iomem *wake_set;
1818
unsigned long flags;
1820
switch (bank->method) {
1821
#ifdef CONFIG_ARCH_OMAP16XX
1822
case METHOD_GPIO_1610:
1823
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1824
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1827
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1828
case METHOD_GPIO_24XX:
1829
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1830
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1833
#ifdef CONFIG_ARCH_OMAP4
1834
case METHOD_GPIO_44XX:
1835
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1836
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1843
spin_lock_irqsave(&bank->lock, flags);
1844
__raw_writel(0xffffffff, wake_clear);
1845
__raw_writel(bank->saved_wakeup, wake_set);
1846
spin_unlock_irqrestore(&bank->lock, flags);
1852
static struct sysdev_class omap_gpio_sysclass = {
1854
.suspend = omap_gpio_suspend,
1855
.resume = omap_gpio_resume,
1858
static struct sys_device omap_gpio_device = {
1860
.cls = &omap_gpio_sysclass,
1865
#ifdef CONFIG_ARCH_OMAP2PLUS
1867
static int workaround_enabled;
1869
void omap2_gpio_prepare_for_idle(int off_mode)
1874
if (cpu_is_omap34xx())
1877
for (i = min; i < gpio_bank_count; i++) {
1878
struct gpio_bank *bank = &gpio_bank[i];
1882
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1883
clk_disable(bank->dbck);
1888
/* If going to OFF, remove triggering for all
1889
* non-wakeup GPIOs. Otherwise spurious IRQs will be
1890
* generated. See OMAP2420 Errata item 1.101. */
1891
if (!(bank->enabled_non_wakeup_gpios))
1894
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1895
bank->saved_datain = __raw_readl(bank->base +
1896
OMAP24XX_GPIO_DATAIN);
1897
l1 = __raw_readl(bank->base +
1898
OMAP24XX_GPIO_FALLINGDETECT);
1899
l2 = __raw_readl(bank->base +
1900
OMAP24XX_GPIO_RISINGDETECT);
1903
if (cpu_is_omap44xx()) {
1904
bank->saved_datain = __raw_readl(bank->base +
1906
l1 = __raw_readl(bank->base +
1907
OMAP4_GPIO_FALLINGDETECT);
1908
l2 = __raw_readl(bank->base +
1909
OMAP4_GPIO_RISINGDETECT);
1912
bank->saved_fallingdetect = l1;
1913
bank->saved_risingdetect = l2;
1914
l1 &= ~bank->enabled_non_wakeup_gpios;
1915
l2 &= ~bank->enabled_non_wakeup_gpios;
1917
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1918
__raw_writel(l1, bank->base +
1919
OMAP24XX_GPIO_FALLINGDETECT);
1920
__raw_writel(l2, bank->base +
1921
OMAP24XX_GPIO_RISINGDETECT);
1924
if (cpu_is_omap44xx()) {
1925
__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1926
__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1932
workaround_enabled = 0;
1935
workaround_enabled = 1;
1938
void omap2_gpio_resume_after_idle(void)
1943
if (cpu_is_omap34xx())
1945
for (i = min; i < gpio_bank_count; i++) {
1946
struct gpio_bank *bank = &gpio_bank[i];
1947
u32 l = 0, gen, gen0, gen1;
1950
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1951
clk_enable(bank->dbck);
1953
if (!workaround_enabled)
1956
if (!(bank->enabled_non_wakeup_gpios))
1959
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1960
__raw_writel(bank->saved_fallingdetect,
1961
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1962
__raw_writel(bank->saved_risingdetect,
1963
bank->base + OMAP24XX_GPIO_RISINGDETECT);
1964
l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1967
if (cpu_is_omap44xx()) {
1968
__raw_writel(bank->saved_fallingdetect,
1969
bank->base + OMAP4_GPIO_FALLINGDETECT);
1970
__raw_writel(bank->saved_risingdetect,
1971
bank->base + OMAP4_GPIO_RISINGDETECT);
1972
l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1975
/* Check if any of the non-wakeup interrupt GPIOs have changed
1976
* state. If so, generate an IRQ by software. This is
1977
* horribly racy, but it's the best we can do to work around
1978
* this silicon bug. */
1979
l ^= bank->saved_datain;
1980
l &= bank->enabled_non_wakeup_gpios;
1983
* No need to generate IRQs for the rising edge for gpio IRQs
1984
* configured with falling edge only; and vice versa.
1986
gen0 = l & bank->saved_fallingdetect;
1987
gen0 &= bank->saved_datain;
1989
gen1 = l & bank->saved_risingdetect;
1990
gen1 &= ~(bank->saved_datain);
1992
/* FIXME: Consider GPIO IRQs with level detections properly! */
1993
gen = l & (~(bank->saved_fallingdetect) &
1994
~(bank->saved_risingdetect));
1995
/* Consider all GPIO IRQs needed to be updated */
2001
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2002
old0 = __raw_readl(bank->base +
2003
OMAP24XX_GPIO_LEVELDETECT0);
2004
old1 = __raw_readl(bank->base +
2005
OMAP24XX_GPIO_LEVELDETECT1);
2006
__raw_writel(old0 | gen, bank->base +
2007
OMAP24XX_GPIO_LEVELDETECT0);
2008
__raw_writel(old1 | gen, bank->base +
2009
OMAP24XX_GPIO_LEVELDETECT1);
2010
__raw_writel(old0, bank->base +
2011
OMAP24XX_GPIO_LEVELDETECT0);
2012
__raw_writel(old1, bank->base +
2013
OMAP24XX_GPIO_LEVELDETECT1);
2016
if (cpu_is_omap44xx()) {
2017
old0 = __raw_readl(bank->base +
2018
OMAP4_GPIO_LEVELDETECT0);
2019
old1 = __raw_readl(bank->base +
2020
OMAP4_GPIO_LEVELDETECT1);
2021
__raw_writel(old0 | l, bank->base +
2022
OMAP4_GPIO_LEVELDETECT0);
2023
__raw_writel(old1 | l, bank->base +
2024
OMAP4_GPIO_LEVELDETECT1);
2025
__raw_writel(old0, bank->base +
2026
OMAP4_GPIO_LEVELDETECT0);
2027
__raw_writel(old1, bank->base +
2028
OMAP4_GPIO_LEVELDETECT1);
2037
#ifdef CONFIG_ARCH_OMAP3
2038
/* save the registers of bank 2-6 */
2039
void omap_gpio_save_context(void)
2043
/* saving banks from 2-6 only since GPIO1 is in WKUP */
2044
for (i = 1; i < gpio_bank_count; i++) {
2045
struct gpio_bank *bank = &gpio_bank[i];
2046
gpio_context[i].irqenable1 =
2047
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2048
gpio_context[i].irqenable2 =
2049
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2050
gpio_context[i].wake_en =
2051
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2052
gpio_context[i].ctrl =
2053
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2054
gpio_context[i].oe =
2055
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
2056
gpio_context[i].leveldetect0 =
2057
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2058
gpio_context[i].leveldetect1 =
2059
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2060
gpio_context[i].risingdetect =
2061
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2062
gpio_context[i].fallingdetect =
2063
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2064
gpio_context[i].dataout =
2065
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2069
/* restore the required registers of bank 2-6 */
2070
void omap_gpio_restore_context(void)
2074
for (i = 1; i < gpio_bank_count; i++) {
2075
struct gpio_bank *bank = &gpio_bank[i];
2076
__raw_writel(gpio_context[i].irqenable1,
2077
bank->base + OMAP24XX_GPIO_IRQENABLE1);
2078
__raw_writel(gpio_context[i].irqenable2,
2079
bank->base + OMAP24XX_GPIO_IRQENABLE2);
2080
__raw_writel(gpio_context[i].wake_en,
2081
bank->base + OMAP24XX_GPIO_WAKE_EN);
2082
__raw_writel(gpio_context[i].ctrl,
2083
bank->base + OMAP24XX_GPIO_CTRL);
2084
__raw_writel(gpio_context[i].oe,
2085
bank->base + OMAP24XX_GPIO_OE);
2086
__raw_writel(gpio_context[i].leveldetect0,
2087
bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2088
__raw_writel(gpio_context[i].leveldetect1,
2089
bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2090
__raw_writel(gpio_context[i].risingdetect,
2091
bank->base + OMAP24XX_GPIO_RISINGDETECT);
2092
__raw_writel(gpio_context[i].fallingdetect,
2093
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2094
__raw_writel(gpio_context[i].dataout,
2095
bank->base + OMAP24XX_GPIO_DATAOUT);
2100
static struct platform_driver omap_gpio_driver = {
2101
.probe = omap_gpio_probe,
2103
.name = "omap_gpio",
2108
* gpio driver register needs to be done before
2109
* machine_init functions access gpio APIs.
2110
* Hence omap_gpio_drv_reg() is a postcore_initcall.
2112
static int __init omap_gpio_drv_reg(void)
2114
return platform_driver_register(&omap_gpio_driver);
2116
postcore_initcall(omap_gpio_drv_reg);
2118
static int __init omap_gpio_sysinit(void)
2124
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2125
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2127
ret = sysdev_class_register(&omap_gpio_sysclass);
2129
ret = sysdev_register(&omap_gpio_device);
2137
arch_initcall(omap_gpio_sysinit);
added
removed
arch/arm/plat-omap/gpio.c
