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Viewing changes to arch/arm/mach-at91/at91sam9g45.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
arch/arm/mach-at91/at91sam9g45.c
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        .type           = CLK_TYPE_PERIPHERAL,
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};
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/* One additional fake clock for ohci */
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static struct clk ohci_clk = {
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        .name           = "ohci_clk",
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        .pmc_mask       = 0,
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        .type           = CLK_TYPE_PERIPHERAL,
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        .parent         = &uhphs_clk,
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};
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/* One additional fake clock for second TC block */
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static struct clk tcb1_clk = {
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        .name           = "tcb1_clk",
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        .pmc_mask       = 0,
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        .type           = CLK_TYPE_PERIPHERAL,
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        .parent         = &tcb0_clk,
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};
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static struct clk *periph_clocks[] __initdata = {
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        &pioA_clk,
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        &pioB_clk,
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        &udphs_clk,
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        &mmc1_clk,
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        // irq0
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        &ohci_clk,
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        &tcb1_clk,
 
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};
 
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static struct clk_lookup periph_clocks_lookups[] = {
 
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        /* One additional fake clock for ohci */
 
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        CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
 
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        CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
 
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        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 
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        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 
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        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
 
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        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
 
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        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 
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        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 
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        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
 
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        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
 
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        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 
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        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 
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};
 
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static struct clk_lookup usart_clocks_lookups[] = {
 
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        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 
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        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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};
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/*
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        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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                clk_register(periph_clocks[i]);
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        clkdev_add_table(periph_clocks_lookups,
 
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                         ARRAY_SIZE(periph_clocks_lookups));
 
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        clkdev_add_table(usart_clocks_lookups,
 
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                         ARRAY_SIZE(usart_clocks_lookups));
 
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        if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
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                clk_register(&vdec_clk);
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        clk_register(&pck1);
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}
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static struct clk_lookup console_clock_lookup;
 
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void __init at91sam9g45_set_console_clock(int id)
 
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{
 
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        if (id >= ARRAY_SIZE(usart_clocks_lookups))
 
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                return;
 
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        console_clock_lookup.con_id = "usart";
 
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        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 
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        clkdev_add(&console_clock_lookup);
 
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}
 
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/* --------------------------------------------------------------------
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 *  GPIO
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 * -------------------------------------------------------------------- */
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 *  AT91SAM9G45 processor initialization
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 * -------------------------------------------------------------------- */
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void __init at91sam9g45_initialize(unsigned long main_clock)
 
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void __init at91sam9g45_map_io(void)
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{
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        /* Map peripherals */
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        iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
 
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}
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void __init at91sam9g45_initialize(unsigned long main_clock)
 
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{
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        at91_arch_reset = at91sam9g45_reset;
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        pm_power_off = at91sam9g45_poweroff;
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        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);